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drm/fourcc: add table describing AMD modifiers bit layout
The table describes how each bit in the u64 value is used. Explicitly state which values a field can take if we have defines for them. Also add a note when a field isn't always populated. Forcing people to update the table when changing the bit layout should make it more obvious when there's a mistake, I hope. If we get to the point where the bit layout gets more complicated, it might be worth it to split the table into multiple tables (e.g. one for GFX8, one for GFX9+, and so on). Signed-off-by: Simon Ser <contact@emersion.fr> Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1114,6 +1114,25 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
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*
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* For multi-plane formats the above surfaces get merged into one plane for
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* each format plane, based on the required alignment only.
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*
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* Bits Parameter Notes
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* ----- ------------------------ ---------------------------------------------
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*
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* 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
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* 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
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* 13 DCC
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* 14 DCC_RETILE
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* 15 DCC_PIPE_ALIGN
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* 16 DCC_INDEPENDENT_64B
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* 17 DCC_INDEPENDENT_128B
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* 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
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* 20 DCC_CONSTANT_ENCODE
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* 23:21 PIPE_XOR_BITS Only for some chips
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* 26:24 BANK_XOR_BITS Only for some chips
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* 29:27 PACKERS Only for some chips
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* 32:30 RB Only for some chips
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* 35:33 PIPE Only for some chips
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* 55:36 - Reserved for future use, must be zero
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*/
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#define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
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