platform/x86/intel/pmc: Add regmap for Tiger Lake H PCH
Tiger Lake H PCH is same as Tiger Lake LP PCH from the driver perspective with the addition of the PSON residency counter. Add regmap for TGP H to add PSON register offsets for Tiger Lake H PCH. Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com> Link: https://lore.kernel.org/r/20231219042216.2592029-3-rajvi.jingar@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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@ -1216,15 +1216,15 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
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X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI, icl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE, cnp_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L, cnp_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, tgl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, tgl_l_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, tgl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, tgl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, tgl_l_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, icl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, tgl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, tgl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, tgl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, tgl_l_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT, tgl_l_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, adl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, tgl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, tgl_l_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, adl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, adl_core_init),
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X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L, mtl_core_init),
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@ -223,6 +223,10 @@ enum ppfear_regs {
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#define TGL_LPM_PRI_OFFSET 0x1C7C
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#define TGL_LPM_NUM_MAPS 6
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/* Tigerlake PSON residency register */
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#define TGL_PSON_RESIDENCY_OFFSET 0x18f8
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#define TGL_PSON_RES_COUNTER_STEP 0x7A
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/* Extended Test Mode Register 3 (CNL and later) */
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#define ETR3_OFFSET 0x1048
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#define ETR3_CF9GR BIT(20)
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@ -507,6 +511,8 @@ int spt_core_init(struct pmc_dev *pmcdev);
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int cnp_core_init(struct pmc_dev *pmcdev);
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int icl_core_init(struct pmc_dev *pmcdev);
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int tgl_core_init(struct pmc_dev *pmcdev);
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int tgl_l_core_init(struct pmc_dev *pmcdev);
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int tgl_core_generic_init(struct pmc_dev *pmcdev, int pch_tp);
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int adl_core_init(struct pmc_dev *pmcdev);
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int mtl_core_init(struct pmc_dev *pmcdev);
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@ -13,6 +13,11 @@
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#define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972"
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#define ACPI_GET_LOW_MODE_REGISTERS 1
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enum pch_type {
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PCH_H,
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PCH_LP
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};
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const struct pmc_bit_map tgl_pfear_map[] = {
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{"PSF9", BIT(0)},
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{"RES_66", BIT(1)},
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@ -205,6 +210,33 @@ const struct pmc_reg_map tgl_reg_map = {
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.etr3_offset = ETR3_OFFSET,
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};
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const struct pmc_reg_map tgl_h_reg_map = {
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.pfear_sts = ext_tgl_pfear_map,
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.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
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.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
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.ltr_show_sts = cnp_ltr_show_map,
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.msr_sts = msr_map,
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.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
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.regmap_length = CNP_PMC_MMIO_REG_LEN,
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.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
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.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
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.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
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.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
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.ltr_ignore_max = TGL_NUM_IP_IGN_ALLOWED,
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.lpm_num_maps = TGL_LPM_NUM_MAPS,
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.lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
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.lpm_sts_latch_en_offset = TGL_LPM_STS_LATCH_EN_OFFSET,
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.lpm_en_offset = TGL_LPM_EN_OFFSET,
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.lpm_priority_offset = TGL_LPM_PRI_OFFSET,
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.lpm_residency_offset = TGL_LPM_RESIDENCY_OFFSET,
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.lpm_sts = tgl_lpm_maps,
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.lpm_status_offset = TGL_LPM_STATUS_OFFSET,
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.lpm_live_status_offset = TGL_LPM_LIVE_STATUS_OFFSET,
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.etr3_offset = ETR3_OFFSET,
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.pson_residency_offset = TGL_PSON_RESIDENCY_OFFSET,
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.pson_residency_counter_step = TGL_PSON_RES_COUNTER_STEP,
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};
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void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)
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{
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struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
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@ -253,12 +285,26 @@ free_acpi_obj:
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ACPI_FREE(out_obj);
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}
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int tgl_l_core_init(struct pmc_dev *pmcdev)
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{
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return tgl_core_generic_init(pmcdev, PCH_LP);
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}
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int tgl_core_init(struct pmc_dev *pmcdev)
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{
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return tgl_core_generic_init(pmcdev, PCH_H);
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}
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int tgl_core_generic_init(struct pmc_dev *pmcdev, int pch_tp)
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{
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struct pmc *pmc = pmcdev->pmcs[PMC_IDX_MAIN];
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int ret;
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pmc->map = &tgl_reg_map;
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if (pch_tp == PCH_H)
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pmc->map = &tgl_h_reg_map;
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else
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pmc->map = &tgl_reg_map;
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ret = get_primary_reg_base(pmc);
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if (ret)
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return ret;
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