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x86/asm: Modernize sync_bitops.h
Add missing instruction suffixes and use rmwcc.h just like was (more or less) recently done for bitops.h as well, see:22636f8c95
: x86/asm: Add instruction suffixes to bitops288e4521f0
: x86/asm: 'Simplify' GEN_*_RMWcc() macros No change in functionality intended. Signed-off-by: Jan Beulich <jbeulich@suse.com> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Juergen Gross <jgross@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/5C9B93870200007800222289@prv1-mh.provo.novell.com [ Cleaned up the changelog a bit. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
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28e3ace70c
commit
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1 changed files with 9 additions and 22 deletions
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@ -14,6 +14,8 @@
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
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*/
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#include <asm/rmwcc.h>
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#define ADDR (*(volatile long *)addr)
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/**
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@ -29,7 +31,7 @@
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*/
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static inline void sync_set_bit(long nr, volatile unsigned long *addr)
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{
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asm volatile("lock; bts %1,%0"
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asm volatile("lock; " __ASM_SIZE(bts) " %1,%0"
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: "+m" (ADDR)
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: "Ir" (nr)
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: "memory");
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@ -47,7 +49,7 @@ static inline void sync_set_bit(long nr, volatile unsigned long *addr)
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*/
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static inline void sync_clear_bit(long nr, volatile unsigned long *addr)
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{
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asm volatile("lock; btr %1,%0"
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asm volatile("lock; " __ASM_SIZE(btr) " %1,%0"
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: "+m" (ADDR)
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: "Ir" (nr)
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: "memory");
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@ -64,7 +66,7 @@ static inline void sync_clear_bit(long nr, volatile unsigned long *addr)
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*/
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static inline void sync_change_bit(long nr, volatile unsigned long *addr)
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{
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asm volatile("lock; btc %1,%0"
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asm volatile("lock; " __ASM_SIZE(btc) " %1,%0"
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: "+m" (ADDR)
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: "Ir" (nr)
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: "memory");
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@ -78,14 +80,9 @@ static inline void sync_change_bit(long nr, volatile unsigned long *addr)
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int sync_test_and_set_bit(long nr, volatile unsigned long *addr)
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static inline bool sync_test_and_set_bit(long nr, volatile unsigned long *addr)
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{
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unsigned char oldbit;
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asm volatile("lock; bts %2,%1\n\tsetc %0"
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: "=qm" (oldbit), "+m" (ADDR)
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: "Ir" (nr) : "memory");
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return oldbit;
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return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(bts), *addr, c, "Ir", nr);
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}
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/**
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@ -98,12 +95,7 @@ static inline int sync_test_and_set_bit(long nr, volatile unsigned long *addr)
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*/
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static inline int sync_test_and_clear_bit(long nr, volatile unsigned long *addr)
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{
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unsigned char oldbit;
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asm volatile("lock; btr %2,%1\n\tsetc %0"
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: "=qm" (oldbit), "+m" (ADDR)
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: "Ir" (nr) : "memory");
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return oldbit;
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return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btr), *addr, c, "Ir", nr);
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}
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/**
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@ -116,12 +108,7 @@ static inline int sync_test_and_clear_bit(long nr, volatile unsigned long *addr)
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*/
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static inline int sync_test_and_change_bit(long nr, volatile unsigned long *addr)
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{
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unsigned char oldbit;
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asm volatile("lock; btc %2,%1\n\tsetc %0"
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: "=qm" (oldbit), "+m" (ADDR)
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: "Ir" (nr) : "memory");
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return oldbit;
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return GEN_BINARY_RMWcc("lock; " __ASM_SIZE(btc), *addr, c, "Ir", nr);
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}
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#define sync_test_bit(nr, addr) test_bit(nr, addr)
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