diff --git a/Documentation/arm/Samsung-S3C24XX/GPIO.txt b/Documentation/arm/Samsung-S3C24XX/GPIO.txt index ea7ccfc4b274..948c8718d967 100644 --- a/Documentation/arm/Samsung-S3C24XX/GPIO.txt +++ b/Documentation/arm/Samsung-S3C24XX/GPIO.txt @@ -51,7 +51,7 @@ PIN Numbers ----------- Each pin has an unique number associated with it in regs-gpio.h, - eg S3C2410_GPA0 or S3C2410_GPF1. These defines are used to tell + eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell the GPIO functions which pin is to be used. @@ -65,11 +65,11 @@ Configuring a pin Eg: - s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); - s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); + s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0); + s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); - which would turn GPA0 into the lowest Address line A0, and set - GPE8 to be connected to the SDIO/MMC controller's SDDAT1 line. + which would turn GPA(0) into the lowest Address line A0, and set + GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line. Reading the current configuration diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index a2cd9beaf37d..38518d450bc0 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -4,6 +4,13 @@ config ARM_GIC config ARM_VIC bool +config ARM_VIC_NR + int + default 2 + help + The maximum number of VICs available in the system, for + power management. + config ICST525 bool diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index b2a781d9ce05..887c6eb3a18a 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -39,11 +40,219 @@ static void vic_unmask_irq(unsigned int irq) writel(1 << irq, base + VIC_INT_ENABLE); } +/** + * vic_init2 - common initialisation code + * @base: Base of the VIC. + * + * Common initialisation code for registeration + * and resume. +*/ +static void vic_init2(void __iomem *base) +{ + int i; + + for (i = 0; i < 16; i++) { + void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); + writel(VIC_VECT_CNTL_ENABLE | i, reg); + } + + writel(32, base + VIC_PL190_DEF_VECT_ADDR); +} + +#if defined(CONFIG_PM) +/** + * struct vic_device - VIC PM device + * @sysdev: The system device which is registered. + * @irq: The IRQ number for the base of the VIC. + * @base: The register base for the VIC. + * @resume_sources: A bitmask of interrupts for resume. + * @resume_irqs: The IRQs enabled for resume. + * @int_select: Save for VIC_INT_SELECT. + * @int_enable: Save for VIC_INT_ENABLE. + * @soft_int: Save for VIC_INT_SOFT. + * @protect: Save for VIC_PROTECT. + */ +struct vic_device { + struct sys_device sysdev; + + void __iomem *base; + int irq; + u32 resume_sources; + u32 resume_irqs; + u32 int_select; + u32 int_enable; + u32 soft_int; + u32 protect; +}; + +/* we cannot allocate memory when VICs are initially registered */ +static struct vic_device vic_devices[CONFIG_ARM_VIC_NR]; + +static inline struct vic_device *to_vic(struct sys_device *sys) +{ + return container_of(sys, struct vic_device, sysdev); +} + +static int vic_id; + +static int vic_class_resume(struct sys_device *dev) +{ + struct vic_device *vic = to_vic(dev); + void __iomem *base = vic->base; + + printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); + + /* re-initialise static settings */ + vic_init2(base); + + writel(vic->int_select, base + VIC_INT_SELECT); + writel(vic->protect, base + VIC_PROTECT); + + /* set the enabled ints and then clear the non-enabled */ + writel(vic->int_enable, base + VIC_INT_ENABLE); + writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); + + /* and the same for the soft-int register */ + + writel(vic->soft_int, base + VIC_INT_SOFT); + writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); + + return 0; +} + +static int vic_class_suspend(struct sys_device *dev, pm_message_t state) +{ + struct vic_device *vic = to_vic(dev); + void __iomem *base = vic->base; + + printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base); + + vic->int_select = readl(base + VIC_INT_SELECT); + vic->int_enable = readl(base + VIC_INT_ENABLE); + vic->soft_int = readl(base + VIC_INT_SOFT); + vic->protect = readl(base + VIC_PROTECT); + + /* set the interrupts (if any) that are used for + * resuming the system */ + + writel(vic->resume_irqs, base + VIC_INT_ENABLE); + writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); + + return 0; +} + +struct sysdev_class vic_class = { + .name = "vic", + .suspend = vic_class_suspend, + .resume = vic_class_resume, +}; + +/** + * vic_pm_register - Register a VIC for later power management control + * @base: The base address of the VIC. + * @irq: The base IRQ for the VIC. + * @resume_sources: bitmask of interrupts allowed for resume sources. + * + * Register the VIC with the system device tree so that it can be notified + * of suspend and resume requests and ensure that the correct actions are + * taken to re-instate the settings on resume. + */ +static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources) +{ + struct vic_device *v; + + if (vic_id >= ARRAY_SIZE(vic_devices)) + printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__); + else { + v = &vic_devices[vic_id]; + v->base = base; + v->resume_sources = resume_sources; + v->irq = irq; + vic_id++; + } +} + +/** + * vic_pm_init - initicall to register VIC pm + * + * This is called via late_initcall() to register + * the resources for the VICs due to the early + * nature of the VIC's registration. +*/ +static int __init vic_pm_init(void) +{ + struct vic_device *dev = vic_devices; + int err; + int id; + + if (vic_id == 0) + return 0; + + err = sysdev_class_register(&vic_class); + if (err) { + printk(KERN_ERR "%s: cannot register class\n", __func__); + return err; + } + + for (id = 0; id < vic_id; id++, dev++) { + dev->sysdev.id = id; + dev->sysdev.cls = &vic_class; + + err = sysdev_register(&dev->sysdev); + if (err) { + printk(KERN_ERR "%s: failed to register device\n", + __func__); + return err; + } + } + + return 0; +} + +late_initcall(vic_pm_init); + +static struct vic_device *vic_from_irq(unsigned int irq) +{ + struct vic_device *v = vic_devices; + unsigned int base_irq = irq & ~31; + int id; + + for (id = 0; id < vic_id; id++, v++) { + if (v->irq == base_irq) + return v; + } + + return NULL; +} + +static int vic_set_wake(unsigned int irq, unsigned int on) +{ + struct vic_device *v = vic_from_irq(irq); + unsigned int off = irq & 31; + + if (!v) + return -EINVAL; + + if (on) + v->resume_irqs |= 1 << off; + else + v->resume_irqs &= ~(1 << off); + + return 0; +} + +#else +static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { } + +#define vic_set_wake NULL +#endif /* CONFIG_PM */ + static struct irq_chip vic_chip = { .name = "VIC", .ack = vic_mask_irq, .mask = vic_mask_irq, .unmask = vic_unmask_irq, + .set_wake = vic_set_wake, }; /** @@ -51,9 +260,10 @@ static struct irq_chip vic_chip = { * @base: iomem base address * @irq_start: starting interrupt number, must be muliple of 32 * @vic_sources: bitmask of interrupt sources to allow + * @resume_sources: bitmask of interrupt sources to allow for resume */ void __init vic_init(void __iomem *base, unsigned int irq_start, - u32 vic_sources) + u32 vic_sources, u32 resume_sources) { unsigned int i; @@ -77,12 +287,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, writel(value, base + VIC_PL190_VECT_ADDR); } - for (i = 0; i < 16; i++) { - void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); - writel(VIC_VECT_CNTL_ENABLE | i, reg); - } - - writel(32, base + VIC_PL190_DEF_VECT_ADDR); + vic_init2(base); for (i = 0; i < 32; i++) { if (vic_sources & (1 << i)) { @@ -94,4 +299,6 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } + + vic_pm_register(base, irq_start, resume_sources); } diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h new file mode 100644 index 000000000000..6a6c66be7f65 --- /dev/null +++ b/arch/arm/include/asm/hardware/pl080.h @@ -0,0 +1,138 @@ +/* arch/arm/include/asm/hardware/pl080.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * ARM PrimeCell PL080 DMA controller + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* Note, there are some Samsung updates to this controller block which + * make it not entierly compatible with the PL080 specification from + * ARM. When in doubt, check the Samsung documentation first. + * + * The Samsung defines are PL080S, and add an extra controll register, + * the ability to move more than 2^11 counts of data and some extra + * OneNAND features. +*/ + +#define PL080_INT_STATUS (0x00) +#define PL080_TC_STATUS (0x04) +#define PL080_TC_CLEAR (0x08) +#define PL080_ERR_STATUS (0x0C) +#define PL080_ERR_CLEAR (0x10) +#define PL080_RAW_TC_STATUS (0x14) +#define PL080_RAW_ERR_STATUS (0x18) +#define PL080_EN_CHAN (0x1c) +#define PL080_SOFT_BREQ (0x20) +#define PL080_SOFT_SREQ (0x24) +#define PL080_SOFT_LBREQ (0x28) +#define PL080_SOFT_LSREQ (0x2C) + +#define PL080_CONFIG (0x30) +#define PL080_CONFIG_M2_BE (1 << 2) +#define PL080_CONFIG_M1_BE (1 << 1) +#define PL080_CONFIG_ENABLE (1 << 0) + +#define PL080_SYNC (0x34) + +/* Per channel configuration registers */ + +#define PL008_Cx_STRIDE (0x20) +#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) +#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20))) +#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20))) +#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20))) +#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20))) +#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20))) +#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20))) +#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20))) + +#define PL080_CH_SRC_ADDR (0x00) +#define PL080_CH_DST_ADDR (0x04) +#define PL080_CH_LLI (0x08) +#define PL080_CH_CONTROL (0x0C) +#define PL080_CH_CONFIG (0x10) +#define PL080S_CH_CONTROL2 (0x10) +#define PL080S_CH_CONFIG (0x14) + +#define PL080_LLI_ADDR_MASK (0x3fffffff << 2) +#define PL080_LLI_ADDR_SHIFT (2) +#define PL080_LLI_LM_AHB2 (1 << 0) + +#define PL080_CONTROL_TC_IRQ_EN (1 << 31) +#define PL080_CONTROL_PROT_MASK (0x7 << 28) +#define PL080_CONTROL_PROT_SHIFT (28) +#define PL080_CONTROL_PROT_SYS (1 << 28) +#define PL080_CONTROL_DST_INCR (1 << 27) +#define PL080_CONTROL_SRC_INCR (1 << 26) +#define PL080_CONTROL_DST_AHB2 (1 << 25) +#define PL080_CONTROL_SRC_AHB2 (1 << 24) +#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21) +#define PL080_CONTROL_DWIDTH_SHIFT (21) +#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18) +#define PL080_CONTROL_SWIDTH_SHIFT (18) +#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15) +#define PL080_CONTROL_DB_SIZE_SHIFT (15) +#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12) +#define PL080_CONTROL_SB_SIZE_SHIFT (12) +#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0) +#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0) + +#define PL080_BSIZE_1 (0x0) +#define PL080_BSIZE_4 (0x1) +#define PL080_BSIZE_8 (0x2) +#define PL080_BSIZE_16 (0x3) +#define PL080_BSIZE_32 (0x4) +#define PL080_BSIZE_64 (0x5) +#define PL080_BSIZE_128 (0x6) +#define PL080_BSIZE_256 (0x7) + +#define PL080_WIDTH_8BIT (0x0) +#define PL080_WIDTH_16BIT (0x1) +#define PL080_WIDTH_32BIT (0x2) + +#define PL080_CONFIG_HALT (1 << 18) +#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */ +#define PL080_CONFIG_LOCK (1 << 16) +#define PL080_CONFIG_TC_IRQ_MASK (1 << 15) +#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14) +#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11) +#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11) +#define PL080_CONFIG_DST_SEL_MASK (0xf << 6) +#define PL080_CONFIG_DST_SEL_SHIFT (6) +#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1) +#define PL080_CONFIG_SRC_SEL_SHIFT (1) +#define PL080_CONFIG_ENABLE (1 << 0) + +#define PL080_FLOW_MEM2MEM (0x0) +#define PL080_FLOW_MEM2PER (0x1) +#define PL080_FLOW_PER2MEM (0x2) +#define PL080_FLOW_SRC2DST (0x3) +#define PL080_FLOW_SRC2DST_DST (0x4) +#define PL080_FLOW_MEM2PER_PER (0x5) +#define PL080_FLOW_PER2MEM_PER (0x6) +#define PL080_FLOW_SRC2DST_SRC (0x7) + +/* DMA linked list chain structure */ + +struct pl080_lli { + u32 src_addr; + u32 dst_addr; + u32 next_lli; + u32 control0; +}; + +struct pl080s_lli { + u32 src_addr; + u32 dst_addr; + u32 next_lli; + u32 control0; + u32 control1; +}; + diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h index f87328d4a180..5d72550a8097 100644 --- a/arch/arm/include/asm/hardware/vic.h +++ b/arch/arm/include/asm/hardware/vic.h @@ -41,7 +41,7 @@ #define VIC_PL192_VECT_ADDR 0xF00 #ifndef __ASSEMBLY__ -void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); +void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources); #endif #endif diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index f477df0e5e4c..204dc5cbd0b8 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -362,8 +362,8 @@ void __init ep93xx_init_irq(void) { int gpio_irq; - vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK); - vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK); + vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); + vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); for (gpio_irq = gpio_to_irq(0); gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c index 79df60c20e70..43da8bb4926b 100644 --- a/arch/arm/mach-netx/generic.c +++ b/arch/arm/mach-netx/generic.c @@ -168,7 +168,7 @@ void __init netx_init_irq(void) { int irq; - vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0); + vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { set_irq_chip(irq, &netx_hif_chip); diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c index 7a7ed4174c8c..6c68e78f3595 100644 --- a/arch/arm/mach-s3c2400/gpio.c +++ b/arch/arm/mach-s3c2400/gpio.c @@ -33,10 +33,10 @@ int s3c2400_gpio_getirq(unsigned int pin) { - if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7) - return -1; /* not valid interrupts */ + if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7)) + return -EINVAL; /* not valid interrupts */ - return (pin - S3C2410_GPE0) + IRQ_EINT0; + return (pin - S3C2410_GPE(0)) + IRQ_EINT0; } EXPORT_SYMBOL(s3c2400_gpio_getirq); diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 63a30d1dd425..41bb65d5b91f 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -59,6 +59,7 @@ config ARCH_H1940 bool "IPAQ H1940" select CPU_S3C2410 select PM_H1940 if PM + select S3C_DEV_USB_HOST help Say Y here if you are using the HP IPAQ H1940 @@ -70,6 +71,7 @@ config PM_H1940 config MACH_N30 bool "Acer N30 family" select CPU_S3C2410 + select S3C_DEV_USB_HOST help Say Y here if you want suppt for the Acer N30, Acer N35, Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. @@ -82,6 +84,7 @@ config ARCH_BAST select MACH_BAST_IDE select S3C24XX_DCLK select ISA + select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec Electronics EB2410ITX development board (also known as BAST) @@ -89,6 +92,7 @@ config ARCH_BAST config MACH_OTOM bool "NexVision OTOM Board" select CPU_S3C2410 + select S3C_DEV_USB_HOST help Say Y here if you are using the Nex Vision OTOM board @@ -96,6 +100,7 @@ config MACH_AML_M5900 bool "AML M5900 Series" select CPU_S3C2410 select PM_SIMTEC if PM + select S3C_DEV_USB_HOST help Say Y here if you are using the American Microsystems M5900 Series @@ -111,6 +116,7 @@ config BAST_PC104_IRQ config MACH_TCT_HAMMER bool "TCT Hammer Board" select CPU_S3C2410 + select S3C_DEV_USB_HOST help Say Y here if you are using the TinCanTools Hammer Board @@ -122,12 +128,14 @@ config MACH_VR1000 select SIMTEC_NOR select MACH_BAST_IDE select CPU_S3C2410 + select S3C_DEV_USB_HOST help Say Y here if you are using the Thorcom VR1000 board. config MACH_QT2410 bool "QT2410" select CPU_S3C2410 + select S3C_DEV_USB_HOST help Say Y here if you are using the Armzone QT2410 diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 440c014e24b3..dbf96e60d992 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -17,14 +17,16 @@ #include #include +#include #include #include -#include +#include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-s3c2410/gpio.c b/arch/arm/mach-s3c2410/gpio.c index 36a3132f39e7..7974afca297c 100644 --- a/arch/arm/mach-s3c2410/gpio.c +++ b/arch/arm/mach-s3c2410/gpio.c @@ -39,12 +39,12 @@ int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, unsigned long flags; unsigned long val; - if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15) - return -1; + if (pin < S3C2410_GPG(8) || pin > S3C2410_GPG(15)) + return -EINVAL; config &= 0xff; - pin -= S3C2410_GPG8; + pin -= S3C2410_GPG(8); reg += pin & ~3; local_irq_save(flags); diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c index 5a6bc56f186b..5aabf117cbb0 100644 --- a/arch/arm/mach-s3c2410/h1940-bluetooth.c +++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c @@ -16,6 +16,8 @@ #include #include #include +#include + #include #include #include @@ -41,9 +43,9 @@ static void h1940bt_enable(int on) h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); /* Reset the chip */ mdelay(10); - s3c2410_gpio_setpin(S3C2410_GPH1, 1); + s3c2410_gpio_setpin(S3C2410_GPH(1), 1); mdelay(10); - s3c2410_gpio_setpin(S3C2410_GPH1, 0); + s3c2410_gpio_setpin(S3C2410_GPH(1), 0); state = 1; } @@ -52,9 +54,9 @@ static void h1940bt_enable(int on) led_trigger_event(bt_led_trigger, 0); #endif - s3c2410_gpio_setpin(S3C2410_GPH1, 1); + s3c2410_gpio_setpin(S3C2410_GPH(1), 1); mdelay(10); - s3c2410_gpio_setpin(S3C2410_GPH1, 0); + s3c2410_gpio_setpin(S3C2410_GPH(1), 0); mdelay(10); h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); @@ -87,14 +89,14 @@ static DEVICE_ATTR(enable, 0644, static int __init h1940bt_probe(struct platform_device *pdev) { /* Configures BT serial port GPIOs */ - s3c2410_gpio_cfgpin(S3C2410_GPH0, S3C2410_GPH0_nCTS0); - s3c2410_gpio_pullup(S3C2410_GPH0, 1); - s3c2410_gpio_cfgpin(S3C2410_GPH1, S3C2410_GPH1_OUTP); - s3c2410_gpio_pullup(S3C2410_GPH1, 1); - s3c2410_gpio_cfgpin(S3C2410_GPH2, S3C2410_GPH2_TXD0); - s3c2410_gpio_pullup(S3C2410_GPH2, 1); - s3c2410_gpio_cfgpin(S3C2410_GPH3, S3C2410_GPH3_RXD0); - s3c2410_gpio_pullup(S3C2410_GPH3, 1); + s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0); + s3c2410_gpio_pullup(S3C2410_GPH(0), 1); + s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_pullup(S3C2410_GPH(1), 1); + s3c2410_gpio_cfgpin(S3C2410_GPH(2), S3C2410_GPH2_TXD0); + s3c2410_gpio_pullup(S3C2410_GPH(2), 1); + s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); + s3c2410_gpio_pullup(S3C2410_GPH(3), 1); #ifdef CONFIG_LEDS_H1940 led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger); diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index 13358ce2128c..c3a2629e0ded 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h @@ -3,7 +3,7 @@ * Copyright (C) 2003,2004,2006 Simtec Electronics * Ben Dooks * - * Samsung S3C241XX DMA support + * Samsung S3C24XX DMA support * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -13,8 +13,8 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H __FILE__ +#include #include -#include #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ @@ -55,9 +55,9 @@ enum dma_ch { /* we have 4 dma channels */ #ifndef CONFIG_CPU_S3C2443 -#define S3C2410_DMA_CHANNELS (4) +#define S3C_DMA_CHANNELS (4) #else -#define S3C2410_DMA_CHANNELS (6) +#define S3C_DMA_CHANNELS (6) #endif /* types */ @@ -68,7 +68,6 @@ enum s3c2410_dma_state { S3C2410_DMA_PAUSED }; - /* enum s3c2410_dma_loadst * * This represents the state of the DMA engine, wrt to the loaded / running @@ -104,32 +103,6 @@ enum s3c2410_dma_loadst { S3C2410_DMALOAD_1LOADED_1RUNNING, }; -enum s3c2410_dma_buffresult { - S3C2410_RES_OK, - S3C2410_RES_ERR, - S3C2410_RES_ABORT -}; - -enum s3c2410_dmasrc { - S3C2410_DMASRC_HW, /* source is memory */ - S3C2410_DMASRC_MEM /* source is hardware */ -}; - -/* enum s3c2410_chan_op - * - * operation codes passed to the DMA code by the user, and also used - * to inform the current channel owner of any changes to the system state -*/ - -enum s3c2410_chan_op { - S3C2410_DMAOP_START, - S3C2410_DMAOP_STOP, - S3C2410_DMAOP_PAUSE, - S3C2410_DMAOP_RESUME, - S3C2410_DMAOP_FLUSH, - S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ - S3C2410_DMAOP_STARTED, /* indicate channel started */ -}; /* flags */ @@ -139,17 +112,14 @@ enum s3c2410_chan_op { /* dma buffer */ -struct s3c2410_dma_client { - char *name; -}; +struct s3c2410_dma_buf; -/* s3c2410_dma_buf_s +/* s3c2410_dma_buf * * internally used buffer structure to describe a queued or running * buffer. */ -struct s3c2410_dma_buf; struct s3c2410_dma_buf { struct s3c2410_dma_buf *next; int magic; /* magic */ @@ -161,20 +131,6 @@ struct s3c2410_dma_buf { /* [1] is this updated for both recv/send modes? */ -struct s3c2410_dma_chan; - -/* s3c2410_dma_cbfn_t - * - * buffer callback routine type -*/ - -typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *, - void *buf, int size, - enum s3c2410_dma_buffresult result); - -typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *, - enum s3c2410_chan_op ); - struct s3c2410_dma_stats { unsigned long loads; unsigned long timeout_longest; @@ -206,10 +162,10 @@ struct s3c2410_dma_chan { /* channel configuration */ enum s3c2410_dmasrc source; + enum dma_ch req_ch; unsigned long dev_addr; unsigned long load_timeout; unsigned int flags; /* channel flags */ - unsigned int hw_cfg; /* last hw config */ struct s3c24xx_dma_map *map; /* channel hw maps */ @@ -236,213 +192,6 @@ struct s3c2410_dma_chan { struct sys_device dev; }; -/* the currently allocated channel information */ -extern struct s3c2410_dma_chan s3c2410_chans[]; - -/* note, we don't really use dma_device_t at the moment */ typedef unsigned long dma_device_t; -/* functions --------------------------------------------------------------- */ - -/* s3c2410_dma_request - * - * request a dma channel exclusivley -*/ - -extern int s3c2410_dma_request(unsigned int channel, - struct s3c2410_dma_client *, void *dev); - - -/* s3c2410_dma_ctrl - * - * change the state of the dma channel -*/ - -extern int s3c2410_dma_ctrl(unsigned int channel, enum s3c2410_chan_op op); - -/* s3c2410_dma_setflags - * - * set the channel's flags to a given state -*/ - -extern int s3c2410_dma_setflags(unsigned int channel, - unsigned int flags); - -/* s3c2410_dma_free - * - * free the dma channel (will also abort any outstanding operations) -*/ - -extern int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *); - -/* s3c2410_dma_enqueue - * - * place the given buffer onto the queue of operations for the channel. - * The buffer must be allocated from dma coherent memory, or the Dcache/WB - * drained before the buffer is given to the DMA system. -*/ - -extern int s3c2410_dma_enqueue(unsigned int channel, void *id, - dma_addr_t data, int size); - -/* s3c2410_dma_config - * - * configure the dma channel -*/ - -extern int s3c2410_dma_config(unsigned int channel, int xferunit, int dcon); - -/* s3c2410_dma_devconfig - * - * configure the device we're talking to -*/ - -extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, - int hwcfg, unsigned long devaddr); - -/* s3c2410_dma_getposition - * - * get the position that the dma transfer is currently at -*/ - -extern int s3c2410_dma_getposition(unsigned int channel, - dma_addr_t *src, dma_addr_t *dest); - -extern int s3c2410_dma_set_opfn(unsigned int, s3c2410_dma_opfn_t rtn); -extern int s3c2410_dma_set_buffdone_fn(unsigned int, s3c2410_dma_cbfn_t rtn); - -/* DMA Register definitions */ - -#define S3C2410_DMA_DISRC (0x00) -#define S3C2410_DMA_DISRCC (0x04) -#define S3C2410_DMA_DIDST (0x08) -#define S3C2410_DMA_DIDSTC (0x0C) -#define S3C2410_DMA_DCON (0x10) -#define S3C2410_DMA_DSTAT (0x14) -#define S3C2410_DMA_DCSRC (0x18) -#define S3C2410_DMA_DCDST (0x1C) -#define S3C2410_DMA_DMASKTRIG (0x20) -#define S3C2412_DMA_DMAREQSEL (0x24) -#define S3C2443_DMA_DMAREQSEL (0x24) - -#define S3C2410_DISRCC_INC (1<<0) -#define S3C2410_DISRCC_APB (1<<1) - -#define S3C2410_DMASKTRIG_STOP (1<<2) -#define S3C2410_DMASKTRIG_ON (1<<1) -#define S3C2410_DMASKTRIG_SWTRIG (1<<0) - -#define S3C2410_DCON_DEMAND (0<<31) -#define S3C2410_DCON_HANDSHAKE (1<<31) -#define S3C2410_DCON_SYNC_PCLK (0<<30) -#define S3C2410_DCON_SYNC_HCLK (1<<30) - -#define S3C2410_DCON_INTREQ (1<<29) - -#define S3C2410_DCON_CH0_XDREQ0 (0<<24) -#define S3C2410_DCON_CH0_UART0 (1<<24) -#define S3C2410_DCON_CH0_SDI (2<<24) -#define S3C2410_DCON_CH0_TIMER (3<<24) -#define S3C2410_DCON_CH0_USBEP1 (4<<24) - -#define S3C2410_DCON_CH1_XDREQ1 (0<<24) -#define S3C2410_DCON_CH1_UART1 (1<<24) -#define S3C2410_DCON_CH1_I2SSDI (2<<24) -#define S3C2410_DCON_CH1_SPI (3<<24) -#define S3C2410_DCON_CH1_USBEP2 (4<<24) - -#define S3C2410_DCON_CH2_I2SSDO (0<<24) -#define S3C2410_DCON_CH2_I2SSDI (1<<24) -#define S3C2410_DCON_CH2_SDI (2<<24) -#define S3C2410_DCON_CH2_TIMER (3<<24) -#define S3C2410_DCON_CH2_USBEP3 (4<<24) - -#define S3C2410_DCON_CH3_UART2 (0<<24) -#define S3C2410_DCON_CH3_SDI (1<<24) -#define S3C2410_DCON_CH3_SPI (2<<24) -#define S3C2410_DCON_CH3_TIMER (3<<24) -#define S3C2410_DCON_CH3_USBEP4 (4<<24) - -#define S3C2410_DCON_SRCSHIFT (24) -#define S3C2410_DCON_SRCMASK (7<<24) - -#define S3C2410_DCON_BYTE (0<<20) -#define S3C2410_DCON_HALFWORD (1<<20) -#define S3C2410_DCON_WORD (2<<20) - -#define S3C2410_DCON_AUTORELOAD (0<<22) -#define S3C2410_DCON_NORELOAD (1<<22) -#define S3C2410_DCON_HWTRIG (1<<23) - -#ifdef CONFIG_CPU_S3C2440 -#define S3C2440_DIDSTC_CHKINT (1<<2) - -#define S3C2440_DCON_CH0_I2SSDO (5<<24) -#define S3C2440_DCON_CH0_PCMIN (6<<24) - -#define S3C2440_DCON_CH1_PCMOUT (5<<24) -#define S3C2440_DCON_CH1_SDI (6<<24) - -#define S3C2440_DCON_CH2_PCMIN (5<<24) -#define S3C2440_DCON_CH2_MICIN (6<<24) - -#define S3C2440_DCON_CH3_MICIN (5<<24) -#define S3C2440_DCON_CH3_PCMOUT (6<<24) -#endif - -#ifdef CONFIG_CPU_S3C2412 - -#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1) - -#define S3C2412_DMAREQSEL_HW (1) - -#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0) -#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1) -#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2) -#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3) -#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4) -#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5) -#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9) -#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10) -#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13) -#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14) -#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15) -#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16) -#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17) -#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18) -#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19) -#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20) -#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21) -#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22) -#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23) -#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24) - -#endif - -#define S3C2443_DMAREQSEL_SRC(x) ((x)<<1) - -#define S3C2443_DMAREQSEL_HW (1) - -#define S3C2443_DMAREQSEL_SPI0TX S3C2443_DMAREQSEL_SRC(0) -#define S3C2443_DMAREQSEL_SPI0RX S3C2443_DMAREQSEL_SRC(1) -#define S3C2443_DMAREQSEL_SPI1TX S3C2443_DMAREQSEL_SRC(2) -#define S3C2443_DMAREQSEL_SPI1RX S3C2443_DMAREQSEL_SRC(3) -#define S3C2443_DMAREQSEL_I2STX S3C2443_DMAREQSEL_SRC(4) -#define S3C2443_DMAREQSEL_I2SRX S3C2443_DMAREQSEL_SRC(5) -#define S3C2443_DMAREQSEL_TIMER S3C2443_DMAREQSEL_SRC(9) -#define S3C2443_DMAREQSEL_SDI S3C2443_DMAREQSEL_SRC(10) -#define S3C2443_DMAREQSEL_XDREQ0 S3C2443_DMAREQSEL_SRC(17) -#define S3C2443_DMAREQSEL_XDREQ1 S3C2443_DMAREQSEL_SRC(18) -#define S3C2443_DMAREQSEL_UART0_0 S3C2443_DMAREQSEL_SRC(19) -#define S3C2443_DMAREQSEL_UART0_1 S3C2443_DMAREQSEL_SRC(20) -#define S3C2443_DMAREQSEL_UART1_0 S3C2443_DMAREQSEL_SRC(21) -#define S3C2443_DMAREQSEL_UART1_1 S3C2443_DMAREQSEL_SRC(22) -#define S3C2443_DMAREQSEL_UART2_0 S3C2443_DMAREQSEL_SRC(23) -#define S3C2443_DMAREQSEL_UART2_1 S3C2443_DMAREQSEL_SRC(24) -#define S3C2443_DMAREQSEL_UART3_0 S3C2443_DMAREQSEL_SRC(25) -#define S3C2443_DMAREQSEL_UART3_1 S3C2443_DMAREQSEL_SRC(26) -#define S3C2443_DMAREQSEL_PCMOUT S3C2443_DMAREQSEL_SRC(27) -#define S3C2443_DMAREQSEL_PCMIN S3C2443_DMAREQSEL_SRC(28) -#define S3C2443_DMAREQSEL_MICIN S3C2443_DMAREQSEL_SRC(29) - #endif /* __ASM_ARCH_DMA_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h index 6c9fbb99ef14..8fe192081d3a 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h @@ -24,7 +24,7 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) { struct s3c_gpio_chip *chip; - if (pin > S3C2410_GPG10) + if (pin > S3C2410_GPG(10)) return NULL; chip = &s3c24xx_gpios[pin/32]; diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h new file mode 100644 index 000000000000..801dff13858d --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h @@ -0,0 +1,103 @@ +/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h + * + * Copyright (c) 2003,2009 Simtec Electronics + * Ben Dooks + * + * S3C2410 - hardware + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* These functions are in the to-be-removed category and it is strongly + * encouraged not to use these in new code. They will be marked deprecated + * very soon. + * + * Most of the functionality can be either replaced by the gpiocfg calls + * for the s3c platform or by the generic GPIOlib API. +*/ + +/* external functions for GPIO support + * + * These allow various different clients to access the same GPIO + * registers without conflicting. If your driver only owns the entire + * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. +*/ + +/* s3c2410_gpio_cfgpin + * + * set the configuration of the given pin to the value passed. + * + * eg: + * s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0); + * s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); +*/ + +extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); + +extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); + +/* s3c2410_gpio_getirq + * + * turn the given pin number into the corresponding IRQ number + * + * returns: + * < 0 = no interrupt for this pin + * >=0 = interrupt number for the pin +*/ + +extern int s3c2410_gpio_getirq(unsigned int pin); + +#ifdef CONFIG_CPU_S3C2400 + +extern int s3c2400_gpio_getirq(unsigned int pin); + +#endif /* CONFIG_CPU_S3C2400 */ + +/* s3c2410_gpio_irqfilter + * + * set the irq filtering on the given pin + * + * on = 0 => disable filtering + * 1 => enable filtering + * + * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with + * width of filter (0 through 63) + * + * +*/ + +extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, + unsigned int config); + +/* s3c2410_gpio_pullup + * + * configure the pull-up control on the given pin + * + * to = 1 => disable the pull-up + * 0 => enable the pull-up + * + * eg; + * + * s3c2410_gpio_pullup(S3C2410_GPB(0), 0); + * s3c2410_gpio_pullup(S3C2410_GPE(8), 0); +*/ + +extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); + +/* s3c2410_gpio_getpull + * + * Read the state of the pull-up on a given pin + * + * return: + * < 0 => error code + * 0 => enabled + * 1 => disabled +*/ + +extern int s3c2410_gpio_getpull(unsigned int pin); + +extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); + +extern unsigned int s3c2410_gpio_getpin(unsigned int pin); diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h index ce1ec69806a1..2edbb9c88ab3 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h @@ -11,6 +11,9 @@ * published by the Free Software Foundation. */ +#ifndef __MACH_GPIONRS_H +#define __MACH_GPIONRS_H + #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) #define S3C2410_GPIO_BANKA (32*0) @@ -21,3 +24,70 @@ #define S3C2410_GPIO_BANKF (32*5) #define S3C2410_GPIO_BANKG (32*6) #define S3C2410_GPIO_BANKH (32*7) + +/* GPIO bank sizes */ +#define S3C2410_GPIO_A_NR (32) +#define S3C2410_GPIO_B_NR (32) +#define S3C2410_GPIO_C_NR (32) +#define S3C2410_GPIO_D_NR (32) +#define S3C2410_GPIO_E_NR (32) +#define S3C2410_GPIO_F_NR (32) +#define S3C2410_GPIO_G_NR (32) +#define S3C2410_GPIO_H_NR (32) + +#if CONFIG_S3C_GPIO_SPACE != 0 +#error CONFIG_S3C_GPIO_SPACE cannot be zero at the moment +#endif + +#define S3C2410_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 0) + +#ifndef __ASSEMBLY__ + +enum s3c_gpio_number { + S3C2410_GPIO_A_START = 0, + S3C2410_GPIO_B_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_A), + S3C2410_GPIO_C_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_B), + S3C2410_GPIO_D_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_C), + S3C2410_GPIO_E_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_D), + S3C2410_GPIO_F_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_E), + S3C2410_GPIO_G_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_F), + S3C2410_GPIO_H_START = S3C2410_GPIO_NEXT(S3C2410_GPIO_G), +}; + +#endif /* __ASSEMBLY__ */ + +/* S3C2410 GPIO number definitions. */ + +#define S3C2410_GPA(_nr) (S3C2410_GPIO_A_START + (_nr)) +#define S3C2410_GPB(_nr) (S3C2410_GPIO_B_START + (_nr)) +#define S3C2410_GPC(_nr) (S3C2410_GPIO_C_START + (_nr)) +#define S3C2410_GPD(_nr) (S3C2410_GPIO_D_START + (_nr)) +#define S3C2410_GPE(_nr) (S3C2410_GPIO_E_START + (_nr)) +#define S3C2410_GPF(_nr) (S3C2410_GPIO_F_START + (_nr)) +#define S3C2410_GPG(_nr) (S3C2410_GPIO_G_START + (_nr)) +#define S3C2410_GPH(_nr) (S3C2410_GPIO_H_START + (_nr)) + +/* compatibility until drivers can be modified */ + +#define S3C2410_GPA0 S3C2410_GPA(0) +#define S3C2410_GPA1 S3C2410_GPA(1) +#define S3C2410_GPA3 S3C2410_GPA(3) +#define S3C2410_GPA7 S3C2410_GPA(7) + +#define S3C2410_GPE0 S3C2410_GPE(0) +#define S3C2410_GPE1 S3C2410_GPE(1) +#define S3C2410_GPE2 S3C2410_GPE(2) +#define S3C2410_GPE3 S3C2410_GPE(3) +#define S3C2410_GPE4 S3C2410_GPE(4) +#define S3C2410_GPE5 S3C2410_GPE(5) +#define S3C2410_GPE6 S3C2410_GPE(6) +#define S3C2410_GPE7 S3C2410_GPE(7) +#define S3C2410_GPE8 S3C2410_GPE(8) +#define S3C2410_GPE9 S3C2410_GPE(9) +#define S3C2410_GPE10 S3C2410_GPE(10) + +#define S3C2410_GPH10 S3C2410_GPH(10) + +#endif /* __MACH_GPIONRS_H */ + diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h index 51a88cf9526b..15f0b3e7ce69 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h @@ -24,5 +24,6 @@ #include #include +#include #define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) diff --git a/arch/arm/mach-s3c2410/include/mach/hardware.h b/arch/arm/mach-s3c2410/include/mach/hardware.h index 74d5a1a4024c..aef5631eac58 100644 --- a/arch/arm/mach-s3c2410/include/mach/hardware.h +++ b/arch/arm/mach-s3c2410/include/mach/hardware.h @@ -15,101 +15,6 @@ #ifndef __ASSEMBLY__ -/* external functions for GPIO support - * - * These allow various different clients to access the same GPIO - * registers without conflicting. If your driver only owns the entire - * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. -*/ - -/* s3c2410_gpio_cfgpin - * - * set the configuration of the given pin to the value passed. - * - * eg: - * s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0); - * s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1); -*/ - -extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); - -extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); - -/* s3c2410_gpio_getirq - * - * turn the given pin number into the corresponding IRQ number - * - * returns: - * < 0 = no interrupt for this pin - * >=0 = interrupt number for the pin -*/ - -extern int s3c2410_gpio_getirq(unsigned int pin); - -/* s3c2410_gpio_irq2pin - * - * turn the given irq number into the corresponding GPIO number - * - * returns: - * < 0 = no pin - * >=0 = gpio pin number -*/ - -extern int s3c2410_gpio_irq2pin(unsigned int irq); - -#ifdef CONFIG_CPU_S3C2400 - -extern int s3c2400_gpio_getirq(unsigned int pin); - -#endif /* CONFIG_CPU_S3C2400 */ - -/* s3c2410_gpio_irqfilter - * - * set the irq filtering on the given pin - * - * on = 0 => disable filtering - * 1 => enable filtering - * - * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with - * width of filter (0 through 63) - * - * -*/ - -extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, - unsigned int config); - -/* s3c2410_gpio_pullup - * - * configure the pull-up control on the given pin - * - * to = 1 => disable the pull-up - * 0 => enable the pull-up - * - * eg; - * - * s3c2410_gpio_pullup(S3C2410_GPB0, 0); - * s3c2410_gpio_pullup(S3C2410_GPE8, 0); -*/ - -extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); - -/* s3c2410_gpio_getpull - * - * Read the state of the pull-up on a given pin - * - * return: - * < 0 => error code - * 0 => enabled - * 1 => disabled -*/ - -extern int s3c2410_gpio_getpull(unsigned int pin); - -extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); - -extern unsigned int s3c2410_gpio_getpin(unsigned int pin); - extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); #ifdef CONFIG_CPU_S3C2440 diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 255fdfeaf957..e99b212cb1ca 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -84,7 +84,6 @@ #define S3C24XX_PA_IRQ S3C2410_PA_IRQ #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL -#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST #define S3C24XX_PA_DMA S3C2410_PA_DMA #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR #define S3C24XX_PA_LCD S3C2410_PA_LCD @@ -102,6 +101,7 @@ #define S3C_PA_IIC S3C2410_PA_IIC #define S3C_PA_UART S3C24XX_PA_UART +#define S3C_PA_USBHOST S3C2410_PA_USBHOST #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 35a03df473fc..b278d0c45ccf 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h @@ -69,104 +69,58 @@ #define S3C2400_GPACON S3C2410_GPIOREG(0x00) #define S3C2400_GPADAT S3C2410_GPIOREG(0x04) -#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) -#define S3C2410_GPA0_OUT (0<<0) #define S3C2410_GPA0_ADDR0 (1<<0) -#define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1) -#define S3C2410_GPA1_OUT (0<<1) #define S3C2410_GPA1_ADDR16 (1<<1) -#define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2) -#define S3C2410_GPA2_OUT (0<<2) #define S3C2410_GPA2_ADDR17 (1<<2) -#define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3) -#define S3C2410_GPA3_OUT (0<<3) #define S3C2410_GPA3_ADDR18 (1<<3) -#define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4) -#define S3C2410_GPA4_OUT (0<<4) #define S3C2410_GPA4_ADDR19 (1<<4) -#define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5) -#define S3C2410_GPA5_OUT (0<<5) #define S3C2410_GPA5_ADDR20 (1<<5) -#define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6) -#define S3C2410_GPA6_OUT (0<<6) #define S3C2410_GPA6_ADDR21 (1<<6) -#define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7) -#define S3C2410_GPA7_OUT (0<<7) #define S3C2410_GPA7_ADDR22 (1<<7) -#define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8) -#define S3C2410_GPA8_OUT (0<<8) #define S3C2410_GPA8_ADDR23 (1<<8) -#define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9) -#define S3C2410_GPA9_OUT (0<<9) #define S3C2410_GPA9_ADDR24 (1<<9) -#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) -#define S3C2410_GPA10_OUT (0<<10) #define S3C2410_GPA10_ADDR25 (1<<10) #define S3C2400_GPA10_SCKE (1<<10) -#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) -#define S3C2410_GPA11_OUT (0<<11) #define S3C2410_GPA11_ADDR26 (1<<11) #define S3C2400_GPA11_nCAS0 (1<<11) -#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) -#define S3C2410_GPA12_OUT (0<<12) #define S3C2410_GPA12_nGCS1 (1<<12) #define S3C2400_GPA12_nCAS1 (1<<12) -#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) -#define S3C2410_GPA13_OUT (0<<13) #define S3C2410_GPA13_nGCS2 (1<<13) #define S3C2400_GPA13_nGCS1 (1<<13) -#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) -#define S3C2410_GPA14_OUT (0<<14) #define S3C2410_GPA14_nGCS3 (1<<14) #define S3C2400_GPA14_nGCS2 (1<<14) -#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) -#define S3C2410_GPA15_OUT (0<<15) #define S3C2410_GPA15_nGCS4 (1<<15) #define S3C2400_GPA15_nGCS3 (1<<15) -#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) -#define S3C2410_GPA16_OUT (0<<16) #define S3C2410_GPA16_nGCS5 (1<<16) #define S3C2400_GPA16_nGCS4 (1<<16) -#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) -#define S3C2410_GPA17_OUT (0<<17) #define S3C2410_GPA17_CLE (1<<17) #define S3C2400_GPA17_nGCS5 (1<<17) -#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) -#define S3C2410_GPA18_OUT (0<<18) #define S3C2410_GPA18_ALE (1<<18) -#define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19) -#define S3C2410_GPA19_OUT (0<<19) #define S3C2410_GPA19_nFWE (1<<19) -#define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20) -#define S3C2410_GPA20_OUT (0<<20) #define S3C2410_GPA20_nFRE (1<<20) -#define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21) -#define S3C2410_GPA21_OUT (0<<21) #define S3C2410_GPA21_nRSTOUT (1<<21) -#define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22) -#define S3C2410_GPA22_OUT (0<<22) #define S3C2410_GPA22_nFCE (1<<22) /* 0x08 and 0x0c are reserved on S3C2410 */ @@ -194,107 +148,69 @@ /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */ -#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) -#define S3C2410_GPB0_INP (0x00 << 0) -#define S3C2410_GPB0_OUTP (0x01 << 0) #define S3C2410_GPB0_TOUT0 (0x02 << 0) #define S3C2400_GPB0_DATA16 (0x02 << 0) -#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) -#define S3C2410_GPB1_INP (0x00 << 2) -#define S3C2410_GPB1_OUTP (0x01 << 2) #define S3C2410_GPB1_TOUT1 (0x02 << 2) #define S3C2400_GPB1_DATA17 (0x02 << 2) -#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) -#define S3C2410_GPB2_INP (0x00 << 4) -#define S3C2410_GPB2_OUTP (0x01 << 4) #define S3C2410_GPB2_TOUT2 (0x02 << 4) #define S3C2400_GPB2_DATA18 (0x02 << 4) #define S3C2400_GPB2_TCLK1 (0x03 << 4) -#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) -#define S3C2410_GPB3_INP (0x00 << 6) -#define S3C2410_GPB3_OUTP (0x01 << 6) #define S3C2410_GPB3_TOUT3 (0x02 << 6) #define S3C2400_GPB3_DATA19 (0x02 << 6) #define S3C2400_GPB3_TXD1 (0x03 << 6) -#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) -#define S3C2410_GPB4_INP (0x00 << 8) -#define S3C2410_GPB4_OUTP (0x01 << 8) #define S3C2410_GPB4_TCLK0 (0x02 << 8) #define S3C2400_GPB4_DATA20 (0x02 << 8) #define S3C2410_GPB4_MASK (0x03 << 8) #define S3C2400_GPB4_RXD1 (0x03 << 8) #define S3C2400_GPB4_MASK (0x03 << 8) -#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) -#define S3C2410_GPB5_INP (0x00 << 10) -#define S3C2410_GPB5_OUTP (0x01 << 10) #define S3C2410_GPB5_nXBACK (0x02 << 10) #define S3C2443_GPB5_XBACK (0x03 << 10) #define S3C2400_GPB5_DATA21 (0x02 << 10) #define S3C2400_GPB5_nCTS1 (0x03 << 10) -#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) -#define S3C2410_GPB6_INP (0x00 << 12) -#define S3C2410_GPB6_OUTP (0x01 << 12) #define S3C2410_GPB6_nXBREQ (0x02 << 12) #define S3C2443_GPB6_XBREQ (0x03 << 12) #define S3C2400_GPB6_DATA22 (0x02 << 12) #define S3C2400_GPB6_nRTS1 (0x03 << 12) -#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) -#define S3C2410_GPB7_INP (0x00 << 14) -#define S3C2410_GPB7_OUTP (0x01 << 14) #define S3C2410_GPB7_nXDACK1 (0x02 << 14) #define S3C2443_GPB7_XDACK1 (0x03 << 14) #define S3C2400_GPB7_DATA23 (0x02 << 14) -#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) -#define S3C2410_GPB8_INP (0x00 << 16) -#define S3C2410_GPB8_OUTP (0x01 << 16) #define S3C2410_GPB8_nXDREQ1 (0x02 << 16) #define S3C2400_GPB8_DATA24 (0x02 << 16) -#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) -#define S3C2410_GPB9_INP (0x00 << 18) -#define S3C2410_GPB9_OUTP (0x01 << 18) #define S3C2410_GPB9_nXDACK0 (0x02 << 18) #define S3C2443_GPB9_XDACK0 (0x03 << 18) #define S3C2400_GPB9_DATA25 (0x02 << 18) #define S3C2400_GPB9_I2SSDI (0x03 << 18) -#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) -#define S3C2410_GPB10_INP (0x00 << 20) -#define S3C2410_GPB10_OUTP (0x01 << 20) #define S3C2410_GPB10_nXDRE0 (0x02 << 20) #define S3C2443_GPB10_XDREQ0 (0x03 << 20) #define S3C2400_GPB10_DATA26 (0x02 << 20) #define S3C2400_GPB10_nSS (0x03 << 20) -#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11) #define S3C2400_GPB11_INP (0x00 << 22) #define S3C2400_GPB11_OUTP (0x01 << 22) #define S3C2400_GPB11_DATA27 (0x02 << 22) -#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12) #define S3C2400_GPB12_INP (0x00 << 24) #define S3C2400_GPB12_OUTP (0x01 << 24) #define S3C2400_GPB12_DATA28 (0x02 << 24) -#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13) #define S3C2400_GPB13_INP (0x00 << 26) #define S3C2400_GPB13_OUTP (0x01 << 26) #define S3C2400_GPB13_DATA29 (0x02 << 26) -#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14) #define S3C2400_GPB14_INP (0x00 << 28) #define S3C2400_GPB14_OUTP (0x01 << 28) #define S3C2400_GPB14_DATA30 (0x02 << 28) -#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15) #define S3C2400_GPB15_INP (0x00 << 30) #define S3C2400_GPB15_OUTP (0x01 << 30) #define S3C2400_GPB15_DATA31 (0x02 << 30) @@ -315,99 +231,51 @@ #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18) #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C) -#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) -#define S3C2410_GPC0_INP (0x00 << 0) -#define S3C2410_GPC0_OUTP (0x01 << 0) #define S3C2410_GPC0_LEND (0x02 << 0) #define S3C2400_GPC0_VD0 (0x02 << 0) -#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) -#define S3C2410_GPC1_INP (0x00 << 2) -#define S3C2410_GPC1_OUTP (0x01 << 2) #define S3C2410_GPC1_VCLK (0x02 << 2) #define S3C2400_GPC1_VD1 (0x02 << 2) -#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) -#define S3C2410_GPC2_INP (0x00 << 4) -#define S3C2410_GPC2_OUTP (0x01 << 4) #define S3C2410_GPC2_VLINE (0x02 << 4) #define S3C2400_GPC2_VD2 (0x02 << 4) -#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) -#define S3C2410_GPC3_INP (0x00 << 6) -#define S3C2410_GPC3_OUTP (0x01 << 6) #define S3C2410_GPC3_VFRAME (0x02 << 6) #define S3C2400_GPC3_VD3 (0x02 << 6) -#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) -#define S3C2410_GPC4_INP (0x00 << 8) -#define S3C2410_GPC4_OUTP (0x01 << 8) #define S3C2410_GPC4_VM (0x02 << 8) #define S3C2400_GPC4_VD4 (0x02 << 8) -#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) -#define S3C2410_GPC5_INP (0x00 << 10) -#define S3C2410_GPC5_OUTP (0x01 << 10) #define S3C2410_GPC5_LCDVF0 (0x02 << 10) #define S3C2400_GPC5_VD5 (0x02 << 10) -#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) -#define S3C2410_GPC6_INP (0x00 << 12) -#define S3C2410_GPC6_OUTP (0x01 << 12) #define S3C2410_GPC6_LCDVF1 (0x02 << 12) #define S3C2400_GPC6_VD6 (0x02 << 12) -#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) -#define S3C2410_GPC7_INP (0x00 << 14) -#define S3C2410_GPC7_OUTP (0x01 << 14) #define S3C2410_GPC7_LCDVF2 (0x02 << 14) #define S3C2400_GPC7_VD7 (0x02 << 14) -#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) -#define S3C2410_GPC8_INP (0x00 << 16) -#define S3C2410_GPC8_OUTP (0x01 << 16) #define S3C2410_GPC8_VD0 (0x02 << 16) #define S3C2400_GPC8_VD8 (0x02 << 16) -#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) -#define S3C2410_GPC9_INP (0x00 << 18) -#define S3C2410_GPC9_OUTP (0x01 << 18) #define S3C2410_GPC9_VD1 (0x02 << 18) #define S3C2400_GPC9_VD9 (0x02 << 18) -#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) -#define S3C2410_GPC10_INP (0x00 << 20) -#define S3C2410_GPC10_OUTP (0x01 << 20) #define S3C2410_GPC10_VD2 (0x02 << 20) #define S3C2400_GPC10_VD10 (0x02 << 20) -#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) -#define S3C2410_GPC11_INP (0x00 << 22) -#define S3C2410_GPC11_OUTP (0x01 << 22) #define S3C2410_GPC11_VD3 (0x02 << 22) #define S3C2400_GPC11_VD11 (0x02 << 22) -#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) -#define S3C2410_GPC12_INP (0x00 << 24) -#define S3C2410_GPC12_OUTP (0x01 << 24) #define S3C2410_GPC12_VD4 (0x02 << 24) #define S3C2400_GPC12_VD12 (0x02 << 24) -#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) -#define S3C2410_GPC13_INP (0x00 << 26) -#define S3C2410_GPC13_OUTP (0x01 << 26) #define S3C2410_GPC13_VD5 (0x02 << 26) #define S3C2400_GPC13_VD13 (0x02 << 26) -#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) -#define S3C2410_GPC14_INP (0x00 << 28) -#define S3C2410_GPC14_OUTP (0x01 << 28) #define S3C2410_GPC14_VD6 (0x02 << 28) #define S3C2400_GPC14_VD14 (0x02 << 28) -#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) -#define S3C2410_GPC15_INP (0x00 << 30) -#define S3C2410_GPC15_OUTP (0x01 << 30) #define S3C2410_GPC15_VD7 (0x02 << 30) #define S3C2400_GPC15_VD15 (0x02 << 30) @@ -432,99 +300,51 @@ #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24) #define S3C2400_GPDUP S3C2410_GPIOREG(0x28) -#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) -#define S3C2410_GPD0_INP (0x00 << 0) -#define S3C2410_GPD0_OUTP (0x01 << 0) #define S3C2410_GPD0_VD8 (0x02 << 0) #define S3C2400_GPD0_VFRAME (0x02 << 0) #define S3C2442_GPD0_nSPICS1 (0x03 << 0) -#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) -#define S3C2410_GPD1_INP (0x00 << 2) -#define S3C2410_GPD1_OUTP (0x01 << 2) #define S3C2410_GPD1_VD9 (0x02 << 2) #define S3C2400_GPD1_VM (0x02 << 2) #define S3C2442_GPD1_SPICLK1 (0x03 << 2) -#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) -#define S3C2410_GPD2_INP (0x00 << 4) -#define S3C2410_GPD2_OUTP (0x01 << 4) #define S3C2410_GPD2_VD10 (0x02 << 4) #define S3C2400_GPD2_VLINE (0x02 << 4) -#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) -#define S3C2410_GPD3_INP (0x00 << 6) -#define S3C2410_GPD3_OUTP (0x01 << 6) #define S3C2410_GPD3_VD11 (0x02 << 6) #define S3C2400_GPD3_VCLK (0x02 << 6) -#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) -#define S3C2410_GPD4_INP (0x00 << 8) -#define S3C2410_GPD4_OUTP (0x01 << 8) #define S3C2410_GPD4_VD12 (0x02 << 8) #define S3C2400_GPD4_LEND (0x02 << 8) -#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) -#define S3C2410_GPD5_INP (0x00 << 10) -#define S3C2410_GPD5_OUTP (0x01 << 10) #define S3C2410_GPD5_VD13 (0x02 << 10) #define S3C2400_GPD5_TOUT0 (0x02 << 10) -#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) -#define S3C2410_GPD6_INP (0x00 << 12) -#define S3C2410_GPD6_OUTP (0x01 << 12) #define S3C2410_GPD6_VD14 (0x02 << 12) #define S3C2400_GPD6_TOUT1 (0x02 << 12) -#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) -#define S3C2410_GPD7_INP (0x00 << 14) -#define S3C2410_GPD7_OUTP (0x01 << 14) #define S3C2410_GPD7_VD15 (0x02 << 14) #define S3C2400_GPD7_TOUT2 (0x02 << 14) -#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) -#define S3C2410_GPD8_INP (0x00 << 16) -#define S3C2410_GPD8_OUTP (0x01 << 16) #define S3C2410_GPD8_VD16 (0x02 << 16) #define S3C2400_GPD8_TOUT3 (0x02 << 16) -#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) -#define S3C2410_GPD9_INP (0x00 << 18) -#define S3C2410_GPD9_OUTP (0x01 << 18) #define S3C2410_GPD9_VD17 (0x02 << 18) #define S3C2400_GPD9_TCLK0 (0x02 << 18) #define S3C2410_GPD9_MASK (0x03 << 18) -#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) -#define S3C2410_GPD10_INP (0x00 << 20) -#define S3C2410_GPD10_OUTP (0x01 << 20) #define S3C2410_GPD10_VD18 (0x02 << 20) #define S3C2400_GPD10_nWAIT (0x02 << 20) -#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) -#define S3C2410_GPD11_INP (0x00 << 22) -#define S3C2410_GPD11_OUTP (0x01 << 22) #define S3C2410_GPD11_VD19 (0x02 << 22) -#define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12) -#define S3C2410_GPD12_INP (0x00 << 24) -#define S3C2410_GPD12_OUTP (0x01 << 24) #define S3C2410_GPD12_VD20 (0x02 << 24) -#define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13) -#define S3C2410_GPD13_INP (0x00 << 26) -#define S3C2410_GPD13_OUTP (0x01 << 26) #define S3C2410_GPD13_VD21 (0x02 << 26) -#define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14) -#define S3C2410_GPD14_INP (0x00 << 28) -#define S3C2410_GPD14_OUTP (0x01 << 28) #define S3C2410_GPD14_VD22 (0x02 << 28) #define S3C2410_GPD14_nSS1 (0x03 << 28) -#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) -#define S3C2410_GPD15_INP (0x00 << 30) -#define S3C2410_GPD15_OUTP (0x01 << 30) #define S3C2410_GPD15_VD23 (0x02 << 30) #define S3C2410_GPD15_nSS0 (0x03 << 30) @@ -550,34 +370,22 @@ #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30) #define S3C2400_GPEUP S3C2410_GPIOREG(0x34) -#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) -#define S3C2410_GPE0_INP (0x00 << 0) -#define S3C2410_GPE0_OUTP (0x01 << 0) #define S3C2410_GPE0_I2SLRCK (0x02 << 0) #define S3C2443_GPE0_AC_nRESET (0x03 << 0) #define S3C2400_GPE0_EINT0 (0x02 << 0) #define S3C2410_GPE0_MASK (0x03 << 0) -#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) -#define S3C2410_GPE1_INP (0x00 << 2) -#define S3C2410_GPE1_OUTP (0x01 << 2) #define S3C2410_GPE1_I2SSCLK (0x02 << 2) #define S3C2443_GPE1_AC_SYNC (0x03 << 2) #define S3C2400_GPE1_EINT1 (0x02 << 2) #define S3C2400_GPE1_nSS (0x03 << 2) #define S3C2410_GPE1_MASK (0x03 << 2) -#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) -#define S3C2410_GPE2_INP (0x00 << 4) -#define S3C2410_GPE2_OUTP (0x01 << 4) #define S3C2410_GPE2_CDCLK (0x02 << 4) #define S3C2443_GPE2_AC_BITCLK (0x03 << 4) #define S3C2400_GPE2_EINT2 (0x02 << 4) #define S3C2400_GPE2_I2SSDI (0x03 << 4) -#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) -#define S3C2410_GPE3_INP (0x00 << 6) -#define S3C2410_GPE3_OUTP (0x01 << 6) #define S3C2410_GPE3_I2SSDI (0x02 << 6) #define S3C2443_GPE3_AC_SDI (0x03 << 6) #define S3C2400_GPE3_EINT3 (0x02 << 6) @@ -585,9 +393,6 @@ #define S3C2410_GPE3_nSS0 (0x03 << 6) #define S3C2410_GPE3_MASK (0x03 << 6) -#define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4) -#define S3C2410_GPE4_INP (0x00 << 8) -#define S3C2410_GPE4_OUTP (0x01 << 8) #define S3C2410_GPE4_I2SSDO (0x02 << 8) #define S3C2443_GPE4_AC_SDO (0x03 << 8) #define S3C2400_GPE4_EINT4 (0x02 << 8) @@ -595,81 +400,48 @@ #define S3C2410_GPE4_I2SSDI (0x03 << 8) #define S3C2410_GPE4_MASK (0x03 << 8) -#define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5) -#define S3C2410_GPE5_INP (0x00 << 10) -#define S3C2410_GPE5_OUTP (0x01 << 10) #define S3C2410_GPE5_SDCLK (0x02 << 10) #define S3C2443_GPE5_SD1_CLK (0x02 << 10) #define S3C2400_GPE5_EINT5 (0x02 << 10) #define S3C2400_GPE5_TCLK1 (0x03 << 10) -#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) -#define S3C2410_GPE6_INP (0x00 << 12) -#define S3C2410_GPE6_OUTP (0x01 << 12) #define S3C2410_GPE6_SDCMD (0x02 << 12) #define S3C2443_GPE6_SD1_CMD (0x02 << 12) #define S3C2443_GPE6_AC_BITCLK (0x03 << 12) #define S3C2400_GPE6_EINT6 (0x02 << 12) -#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) -#define S3C2410_GPE7_INP (0x00 << 14) -#define S3C2410_GPE7_OUTP (0x01 << 14) #define S3C2410_GPE7_SDDAT0 (0x02 << 14) #define S3C2443_GPE5_SD1_DAT0 (0x02 << 14) #define S3C2443_GPE7_AC_SDI (0x03 << 14) #define S3C2400_GPE7_EINT7 (0x02 << 14) -#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) -#define S3C2410_GPE8_INP (0x00 << 16) -#define S3C2410_GPE8_OUTP (0x01 << 16) #define S3C2410_GPE8_SDDAT1 (0x02 << 16) #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16) #define S3C2443_GPE8_AC_SDO (0x03 << 16) #define S3C2400_GPE8_nXDACK0 (0x02 << 16) -#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) -#define S3C2410_GPE9_INP (0x00 << 18) -#define S3C2410_GPE9_OUTP (0x01 << 18) #define S3C2410_GPE9_SDDAT2 (0x02 << 18) #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18) #define S3C2443_GPE9_AC_SYNC (0x03 << 18) #define S3C2400_GPE9_nXDACK1 (0x02 << 18) #define S3C2400_GPE9_nXBACK (0x03 << 18) -#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) -#define S3C2410_GPE10_INP (0x00 << 20) -#define S3C2410_GPE10_OUTP (0x01 << 20) #define S3C2410_GPE10_SDDAT3 (0x02 << 20) #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20) #define S3C2443_GPE10_AC_nRESET (0x03 << 20) #define S3C2400_GPE10_nXDREQ0 (0x02 << 20) -#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) -#define S3C2410_GPE11_INP (0x00 << 22) -#define S3C2410_GPE11_OUTP (0x01 << 22) #define S3C2410_GPE11_SPIMISO0 (0x02 << 22) #define S3C2400_GPE11_nXDREQ1 (0x02 << 22) #define S3C2400_GPE11_nXBREQ (0x03 << 22) -#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) -#define S3C2410_GPE12_INP (0x00 << 24) -#define S3C2410_GPE12_OUTP (0x01 << 24) #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24) -#define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13) -#define S3C2410_GPE13_INP (0x00 << 26) -#define S3C2410_GPE13_OUTP (0x01 << 26) #define S3C2410_GPE13_SPICLK0 (0x02 << 26) -#define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14) -#define S3C2410_GPE14_INP (0x00 << 28) -#define S3C2410_GPE14_OUTP (0x01 << 28) #define S3C2410_GPE14_IICSCL (0x02 << 28) #define S3C2410_GPE14_MASK (0x03 << 28) -#define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15) -#define S3C2410_GPE15_INP (0x00 << 30) -#define S3C2410_GPE15_OUTP (0x01 << 30) #define S3C2410_GPE15_IICSDA (0x02 << 30) #define S3C2410_GPE15_MASK (0x03 << 30) @@ -705,55 +477,31 @@ #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C) #define S3C2400_GPFUP S3C2410_GPIOREG(0x40) -#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) -#define S3C2410_GPF0_INP (0x00 << 0) -#define S3C2410_GPF0_OUTP (0x01 << 0) #define S3C2410_GPF0_EINT0 (0x02 << 0) #define S3C2400_GPF0_RXD0 (0x02 << 0) -#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) -#define S3C2410_GPF1_INP (0x00 << 2) -#define S3C2410_GPF1_OUTP (0x01 << 2) #define S3C2410_GPF1_EINT1 (0x02 << 2) #define S3C2400_GPF1_RXD1 (0x02 << 2) #define S3C2400_GPF1_IICSDA (0x03 << 2) -#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) -#define S3C2410_GPF2_INP (0x00 << 4) -#define S3C2410_GPF2_OUTP (0x01 << 4) #define S3C2410_GPF2_EINT2 (0x02 << 4) #define S3C2400_GPF2_TXD0 (0x02 << 4) -#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) -#define S3C2410_GPF3_INP (0x00 << 6) -#define S3C2410_GPF3_OUTP (0x01 << 6) #define S3C2410_GPF3_EINT3 (0x02 << 6) #define S3C2400_GPF3_TXD1 (0x02 << 6) #define S3C2400_GPF3_IICSCL (0x03 << 6) -#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) -#define S3C2410_GPF4_INP (0x00 << 8) -#define S3C2410_GPF4_OUTP (0x01 << 8) #define S3C2410_GPF4_EINT4 (0x02 << 8) #define S3C2400_GPF4_nRTS0 (0x02 << 8) #define S3C2400_GPF4_nXBACK (0x03 << 8) -#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) -#define S3C2410_GPF5_INP (0x00 << 10) -#define S3C2410_GPF5_OUTP (0x01 << 10) #define S3C2410_GPF5_EINT5 (0x02 << 10) #define S3C2400_GPF5_nCTS0 (0x02 << 10) #define S3C2400_GPF5_nXBREQ (0x03 << 10) -#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) -#define S3C2410_GPF6_INP (0x00 << 12) -#define S3C2410_GPF6_OUTP (0x01 << 12) #define S3C2410_GPF6_EINT6 (0x02 << 12) #define S3C2400_GPF6_CLKOUT (0x02 << 12) -#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) -#define S3C2410_GPF7_INP (0x00 << 14) -#define S3C2410_GPF7_OUTP (0x01 << 14) #define S3C2410_GPF7_EINT7 (0x02 << 14) #define S3C2410_GPF_PUPDIS(x) (1<<(x)) @@ -778,117 +526,69 @@ #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48) #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C) -#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) -#define S3C2410_GPG0_INP (0x00 << 0) -#define S3C2410_GPG0_OUTP (0x01 << 0) #define S3C2410_GPG0_EINT8 (0x02 << 0) #define S3C2400_GPG0_I2SLRCK (0x02 << 0) -#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) -#define S3C2410_GPG1_INP (0x00 << 2) -#define S3C2410_GPG1_OUTP (0x01 << 2) #define S3C2410_GPG1_EINT9 (0x02 << 2) #define S3C2400_GPG1_I2SSCLK (0x02 << 2) -#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) -#define S3C2410_GPG2_INP (0x00 << 4) -#define S3C2410_GPG2_OUTP (0x01 << 4) #define S3C2410_GPG2_EINT10 (0x02 << 4) #define S3C2410_GPG2_nSS0 (0x03 << 4) #define S3C2400_GPG2_CDCLK (0x02 << 4) -#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) -#define S3C2410_GPG3_INP (0x00 << 6) -#define S3C2410_GPG3_OUTP (0x01 << 6) #define S3C2410_GPG3_EINT11 (0x02 << 6) #define S3C2410_GPG3_nSS1 (0x03 << 6) #define S3C2400_GPG3_I2SSDO (0x02 << 6) #define S3C2400_GPG3_I2SSDI (0x03 << 6) -#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) -#define S3C2410_GPG4_INP (0x00 << 8) -#define S3C2410_GPG4_OUTP (0x01 << 8) #define S3C2410_GPG4_EINT12 (0x02 << 8) #define S3C2400_GPG4_MMCCLK (0x02 << 8) #define S3C2400_GPG4_I2SSDI (0x03 << 8) #define S3C2410_GPG4_LCDPWREN (0x03 << 8) #define S3C2443_GPG4_LCDPWRDN (0x03 << 8) -#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) -#define S3C2410_GPG5_INP (0x00 << 10) -#define S3C2410_GPG5_OUTP (0x01 << 10) #define S3C2410_GPG5_EINT13 (0x02 << 10) #define S3C2400_GPG5_MMCCMD (0x02 << 10) #define S3C2400_GPG5_IICSDA (0x03 << 10) #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */ -#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) -#define S3C2410_GPG6_INP (0x00 << 12) -#define S3C2410_GPG6_OUTP (0x01 << 12) #define S3C2410_GPG6_EINT14 (0x02 << 12) #define S3C2400_GPG6_MMCDAT (0x02 << 12) #define S3C2400_GPG6_IICSCL (0x03 << 12) #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) -#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) -#define S3C2410_GPG7_INP (0x00 << 14) -#define S3C2410_GPG7_OUTP (0x01 << 14) #define S3C2410_GPG7_EINT15 (0x02 << 14) #define S3C2410_GPG7_SPICLK1 (0x03 << 14) #define S3C2400_GPG7_SPIMISO (0x02 << 14) #define S3C2400_GPG7_IICSDA (0x03 << 14) -#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) -#define S3C2410_GPG8_INP (0x00 << 16) -#define S3C2410_GPG8_OUTP (0x01 << 16) #define S3C2410_GPG8_EINT16 (0x02 << 16) #define S3C2400_GPG8_SPIMOSI (0x02 << 16) #define S3C2400_GPG8_IICSCL (0x03 << 16) -#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) -#define S3C2410_GPG9_INP (0x00 << 18) -#define S3C2410_GPG9_OUTP (0x01 << 18) #define S3C2410_GPG9_EINT17 (0x02 << 18) #define S3C2400_GPG9_SPICLK (0x02 << 18) #define S3C2400_GPG9_MMCCLK (0x03 << 18) -#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) -#define S3C2410_GPG10_INP (0x00 << 20) -#define S3C2410_GPG10_OUTP (0x01 << 20) #define S3C2410_GPG10_EINT18 (0x02 << 20) -#define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11) -#define S3C2410_GPG11_INP (0x00 << 22) -#define S3C2410_GPG11_OUTP (0x01 << 22) #define S3C2410_GPG11_EINT19 (0x02 << 22) #define S3C2410_GPG11_TCLK1 (0x03 << 22) #define S3C2443_GPG11_CF_nIREQ (0x03 << 22) -#define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12) -#define S3C2410_GPG12_INP (0x00 << 24) -#define S3C2410_GPG12_OUTP (0x01 << 24) #define S3C2410_GPG12_EINT20 (0x02 << 24) #define S3C2410_GPG12_XMON (0x03 << 24) #define S3C2442_GPG12_nSPICS0 (0x03 << 24) #define S3C2443_GPG12_nINPACK (0x03 << 24) -#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) -#define S3C2410_GPG13_INP (0x00 << 26) -#define S3C2410_GPG13_OUTP (0x01 << 26) #define S3C2410_GPG13_EINT21 (0x02 << 26) #define S3C2410_GPG13_nXPON (0x03 << 26) #define S3C2443_GPG13_CF_nREG (0x03 << 26) -#define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14) -#define S3C2410_GPG14_INP (0x00 << 28) -#define S3C2410_GPG14_OUTP (0x01 << 28) #define S3C2410_GPG14_EINT22 (0x02 << 28) #define S3C2410_GPG14_YMON (0x03 << 28) #define S3C2443_GPG14_CF_RESET (0x03 << 28) -#define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15) -#define S3C2410_GPG15_INP (0x00 << 30) -#define S3C2410_GPG15_OUTP (0x01 << 30) #define S3C2410_GPG15_EINT23 (0x02 << 30) #define S3C2410_GPG15_nYPON (0x03 << 30) #define S3C2443_GPG15_CF_PWR (0x03 << 30) @@ -907,62 +607,29 @@ #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74) #define S3C2410_GPHUP S3C2410_GPIOREG(0x78) -#define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0) -#define S3C2410_GPH0_INP (0x00 << 0) -#define S3C2410_GPH0_OUTP (0x01 << 0) #define S3C2410_GPH0_nCTS0 (0x02 << 0) -#define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1) -#define S3C2410_GPH1_INP (0x00 << 2) -#define S3C2410_GPH1_OUTP (0x01 << 2) #define S3C2410_GPH1_nRTS0 (0x02 << 2) -#define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2) -#define S3C2410_GPH2_INP (0x00 << 4) -#define S3C2410_GPH2_OUTP (0x01 << 4) #define S3C2410_GPH2_TXD0 (0x02 << 4) -#define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3) -#define S3C2410_GPH3_INP (0x00 << 6) -#define S3C2410_GPH3_OUTP (0x01 << 6) #define S3C2410_GPH3_RXD0 (0x02 << 6) -#define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4) -#define S3C2410_GPH4_INP (0x00 << 8) -#define S3C2410_GPH4_OUTP (0x01 << 8) #define S3C2410_GPH4_TXD1 (0x02 << 8) -#define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5) -#define S3C2410_GPH5_INP (0x00 << 10) -#define S3C2410_GPH5_OUTP (0x01 << 10) #define S3C2410_GPH5_RXD1 (0x02 << 10) -#define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6) -#define S3C2410_GPH6_INP (0x00 << 12) -#define S3C2410_GPH6_OUTP (0x01 << 12) #define S3C2410_GPH6_TXD2 (0x02 << 12) #define S3C2410_GPH6_nRTS1 (0x03 << 12) -#define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7) -#define S3C2410_GPH7_INP (0x00 << 14) -#define S3C2410_GPH7_OUTP (0x01 << 14) #define S3C2410_GPH7_RXD2 (0x02 << 14) #define S3C2410_GPH7_nCTS1 (0x03 << 14) -#define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8) -#define S3C2410_GPH8_INP (0x00 << 16) -#define S3C2410_GPH8_OUTP (0x01 << 16) #define S3C2410_GPH8_UCLK (0x02 << 16) -#define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9) -#define S3C2410_GPH9_INP (0x00 << 18) -#define S3C2410_GPH9_OUTP (0x01 << 18) #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) #define S3C2442_GPH9_nSPICS0 (0x03 << 18) -#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) -#define S3C2410_GPH10_INP (0x00 << 20) -#define S3C2410_GPH10_OUTP (0x01 << 20) #define S3C2410_GPH10_CLKOUT1 (0x02 << 20) /* The S3C2412 and S3C2413 move the GPJ register set to after diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h index b8687f71c304..6faadcee7729 100644 --- a/arch/arm/mach-s3c2410/include/mach/system-reset.h +++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h @@ -11,21 +11,13 @@ */ #include -#include - -#include -#include - -#include -#include +#include extern void (*s3c24xx_reset_hook)(void); static void arch_reset(char mode, const char *cmd) { - struct clk *wdtclk; - if (mode == 's') { cpu_reset(0); } @@ -33,31 +25,7 @@ arch_reset(char mode, const char *cmd) if (s3c24xx_reset_hook) s3c24xx_reset_hook(); - printk("arch_reset: attempting watchdog reset\n"); - - __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ - - wdtclk = clk_get(NULL, "watchdog"); - if (!IS_ERR(wdtclk)) { - clk_enable(wdtclk); - } else - printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__); - - /* put initial values into count and data */ - __raw_writel(0x80, S3C2410_WTCNT); - __raw_writel(0x80, S3C2410_WTDAT); - - /* set the watchdog to go and reset... */ - __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN | - S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON); - - /* wait for reset to assert... */ - mdelay(500); - - printk(KERN_ERR "Watchdog reset failed to assert reset\n"); - - /* delay to allow the serial port to show the message */ - mdelay(50); + arch_wdt_reset(); /* we'll take a jump through zero as a poor second */ cpu_reset(0); diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index 6d6995afeb43..06a84adfb13f 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -224,8 +225,8 @@ static void amlm5900_init_pm(void) } else { enable_irq_wake(IRQ_EINT9); /* configure the suspend/resume status pin */ - s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); - s3c2410_gpio_pullup(S3C2410_GPF2, 0); + s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_pullup(S3C2410_GPF(2), 0); } } static void __init amlm5900_init(void) diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 8637dea5e150..ce3baba2cd7f 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -212,15 +213,15 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { static int bast_pm_suspend(struct sys_device *sd, pm_message_t state) { /* ensure that an nRESET is not generated on resume. */ - s3c2410_gpio_setpin(S3C2410_GPA21, 1); - s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); + s3c2410_gpio_setpin(S3C2410_GPA(21), 1); + s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT); return 0; } static int bast_pm_resume(struct sys_device *sd) { - s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); + s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); return 0; } @@ -591,8 +592,6 @@ static void __init bast_map_io(void) s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c24xx_init_clocks(0); s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); - - usb_simtec_init(); } static void __init bast_init(void) @@ -607,6 +606,7 @@ static void __init bast_init(void) i2c_register_board_info(0, bast_i2c_devs, ARRAY_SIZE(bast_i2c_devs)); + usb_simtec_init(); nor_simtec_init(); } diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 7a7c4da4c256..d9cd5ddecf4a 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -127,7 +127,7 @@ static void h1940_udc_pullup(enum s3c2410_udc_cmd_e cmd) static struct s3c2410_udc_mach_info h1940_udc_cfg __initdata = { .udc_command = h1940_udc_pullup, - .vbus_pin = S3C2410_GPG5, + .vbus_pin = S3C2410_GPG(5), .vbus_pin_inverted = 1, }; diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 2b83f8707710..0f6ed61af415 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -85,10 +86,10 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd) { switch (cmd) { case S3C2410_UDC_P_ENABLE : - s3c2410_gpio_setpin(S3C2410_GPB3, 1); + s3c2410_gpio_setpin(S3C2410_GPB(3), 1); break; case S3C2410_UDC_P_DISABLE : - s3c2410_gpio_setpin(S3C2410_GPB3, 0); + s3c2410_gpio_setpin(S3C2410_GPB(3), 0); break; case S3C2410_UDC_P_RESET : break; @@ -99,55 +100,55 @@ static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd) static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = { .udc_command = n30_udc_pullup, - .vbus_pin = S3C2410_GPG1, + .vbus_pin = S3C2410_GPG(1), .vbus_pin_inverted = 0, }; static struct gpio_keys_button n30_buttons[] = { { - .gpio = S3C2410_GPF0, + .gpio = S3C2410_GPF(0), .code = KEY_POWER, .desc = "Power", .active_low = 0, }, { - .gpio = S3C2410_GPG9, + .gpio = S3C2410_GPG(9), .code = KEY_UP, .desc = "Thumbwheel Up", .active_low = 0, }, { - .gpio = S3C2410_GPG8, + .gpio = S3C2410_GPG(8), .code = KEY_DOWN, .desc = "Thumbwheel Down", .active_low = 0, }, { - .gpio = S3C2410_GPG7, + .gpio = S3C2410_GPG(7), .code = KEY_ENTER, .desc = "Thumbwheel Press", .active_low = 0, }, { - .gpio = S3C2410_GPF7, + .gpio = S3C2410_GPF(7), .code = KEY_HOMEPAGE, .desc = "Home", .active_low = 0, }, { - .gpio = S3C2410_GPF6, + .gpio = S3C2410_GPF(6), .code = KEY_CALENDAR, .desc = "Calendar", .active_low = 0, }, { - .gpio = S3C2410_GPF5, + .gpio = S3C2410_GPF(5), .code = KEY_ADDRESSBOOK, .desc = "Contacts", .active_low = 0, }, { - .gpio = S3C2410_GPF4, + .gpio = S3C2410_GPF(4), .code = KEY_MAIL, .desc = "Mail", .active_low = 0, @@ -169,73 +170,73 @@ static struct platform_device n30_button_device = { static struct gpio_keys_button n35_buttons[] = { { - .gpio = S3C2410_GPF0, + .gpio = S3C2410_GPF(0), .code = KEY_POWER, .desc = "Power", .active_low = 0, }, { - .gpio = S3C2410_GPG9, + .gpio = S3C2410_GPG(9), .code = KEY_UP, .desc = "Joystick Up", .active_low = 0, }, { - .gpio = S3C2410_GPG8, + .gpio = S3C2410_GPG(8), .code = KEY_DOWN, .desc = "Joystick Down", .active_low = 0, }, { - .gpio = S3C2410_GPG6, + .gpio = S3C2410_GPG(6), .code = KEY_DOWN, .desc = "Joystick Left", .active_low = 0, }, { - .gpio = S3C2410_GPG5, + .gpio = S3C2410_GPG(5), .code = KEY_DOWN, .desc = "Joystick Right", .active_low = 0, }, { - .gpio = S3C2410_GPG7, + .gpio = S3C2410_GPG(7), .code = KEY_ENTER, .desc = "Joystick Press", .active_low = 0, }, { - .gpio = S3C2410_GPF7, + .gpio = S3C2410_GPF(7), .code = KEY_HOMEPAGE, .desc = "Home", .active_low = 0, }, { - .gpio = S3C2410_GPF6, + .gpio = S3C2410_GPF(6), .code = KEY_CALENDAR, .desc = "Calendar", .active_low = 0, }, { - .gpio = S3C2410_GPF5, + .gpio = S3C2410_GPF(5), .code = KEY_ADDRESSBOOK, .desc = "Contacts", .active_low = 0, }, { - .gpio = S3C2410_GPF4, + .gpio = S3C2410_GPF(4), .code = KEY_MAIL, .desc = "Mail", .active_low = 0, }, { - .gpio = S3C2410_GPF3, + .gpio = S3C2410_GPF(3), .code = SW_RADIO, .desc = "GPS Antenna", .active_low = 0, }, { - .gpio = S3C2410_GPG2, + .gpio = S3C2410_GPG(2), .code = SW_HEADPHONE_INSERT, .desc = "Headphone", .active_low = 0, @@ -259,7 +260,7 @@ static struct platform_device n35_button_device = { /* This is the bluetooth LED on the device. */ static struct s3c24xx_led_platdata n30_blue_led_pdata = { .name = "blue_led", - .gpio = S3C2410_GPG6, + .gpio = S3C2410_GPG(6), .def_trigger = "", }; @@ -270,7 +271,7 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = { static struct s3c24xx_led_platdata n30_warning_led_pdata = { .name = "warning_led", .flags = S3C24XX_LEDF_ACTLOW, - .gpio = S3C2410_GPD9, + .gpio = S3C2410_GPD(9), .def_trigger = "", }; diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 9f1ba9b63f70..2cc9849eb448 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -198,7 +199,7 @@ static struct platform_device qt2410_cs89x0 = { /* LED */ static struct s3c24xx_led_platdata qt2410_pdata_led = { - .gpio = S3C2410_GPB0, + .gpio = S3C2410_GPB(0), .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, .name = "led", .def_trigger = "timer", @@ -218,18 +219,18 @@ static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs) { switch (cs) { case BITBANG_CS_ACTIVE: - s3c2410_gpio_setpin(S3C2410_GPB5, 0); + s3c2410_gpio_setpin(S3C2410_GPB(5), 0); break; case BITBANG_CS_INACTIVE: - s3c2410_gpio_setpin(S3C2410_GPB5, 1); + s3c2410_gpio_setpin(S3C2410_GPB(5), 1); break; } } static struct s3c2410_spigpio_info spi_gpio_cfg = { - .pin_clk = S3C2410_GPG7, - .pin_mosi = S3C2410_GPG6, - .pin_miso = S3C2410_GPG5, + .pin_clk = S3C2410_GPG(7), + .pin_mosi = S3C2410_GPG(6), + .pin_miso = S3C2410_GPG(5), .chip_select = &spi_gpio_cs, }; @@ -346,13 +347,13 @@ static void __init qt2410_machine_init(void) } s3c24xx_fb_set_platdata(&qt2410_fb_info); - s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPB0, 1); + s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPB(0), 1); s3c24xx_udc_set_platdata(&qt2410_udc_cfg); s3c_i2c0_set_platdata(NULL); - s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_cfgpin(S3C2410_GPB(5), S3C2410_GPIO_OUTPUT); platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); s3c_pm_init(); diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 61a1ea9c5c5c..1628cc773a2c 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -277,19 +278,19 @@ static struct platform_device vr1000_dm9k1 = { static struct s3c24xx_led_platdata vr1000_led1_pdata = { .name = "led1", - .gpio = S3C2410_GPB0, + .gpio = S3C2410_GPB(0), .def_trigger = "", }; static struct s3c24xx_led_platdata vr1000_led2_pdata = { .name = "led2", - .gpio = S3C2410_GPB1, + .gpio = S3C2410_GPB(1), .def_trigger = "", }; static struct s3c24xx_led_platdata vr1000_led3_pdata = { .name = "led3", - .gpio = S3C2410_GPB2, + .gpio = S3C2410_GPB(2), .def_trigger = "", }; @@ -355,8 +356,8 @@ static struct clk *vr1000_clocks[] __initdata = { static void vr1000_power_off(void) { - s3c2410_gpio_cfgpin(S3C2410_GPB9, S3C2410_GPB9_OUTP); - s3c2410_gpio_setpin(S3C2410_GPB9, 1); + s3c2410_gpio_cfgpin(S3C2410_GPB(9), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPB(9), 1); } static void __init vr1000_map_io(void) diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 87fc481d92d4..143e08a599d4 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -76,7 +77,7 @@ static void s3c2410_pm_prepare(void) } if ( machine_is_aml_m5900() ) - s3c2410_gpio_setpin(S3C2410_GPF2, 1); + s3c2410_gpio_setpin(S3C2410_GPF(2), 1); } @@ -91,7 +92,7 @@ static int s3c2410_pm_resume(struct sys_device *dev) __raw_writel(tmp, S3C2410_GSTATUS2); if ( machine_is_aml_m5900() ) - s3c2410_gpio_setpin(S3C2410_GPF2, 0); + s3c2410_gpio_setpin(S3C2410_GPF(2), 0); return 0; } diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index 8331e8d97e20..6cd9377ddb82 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c @@ -18,9 +18,11 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -29,7 +31,6 @@ #include #include -#include #include #include @@ -53,9 +54,9 @@ usb_simtec_powercontrol(int port, int to) power_state[port] = to; if (power_state[0] && power_state[1]) - s3c2410_gpio_setpin(S3C2410_GPB4, 0); + gpio_set_value(S3C2410_GPB(4), 0); else - s3c2410_gpio_setpin(S3C2410_GPB4, 1); + gpio_set_value(S3C2410_GPB(4), 1); } static irqreturn_t @@ -63,7 +64,7 @@ usb_simtec_ocirq(int irq, void *pw) { struct s3c2410_hcd_info *info = pw; - if (s3c2410_gpio_getpin(S3C2410_GPG10) == 0) { + if (gpio_get_value(S3C2410_GPG(10)) == 0) { pr_debug("usb_simtec: over-current irq (oc detected)\n"); s3c2410_usb_report_oc(info, 3); } else { @@ -106,10 +107,27 @@ static struct s3c2410_hcd_info usb_simtec_info = { int usb_simtec_init(void) { - printk("USB Power Control, (c) 2004 Simtec Electronics\n"); - s3c_device_usb.dev.platform_data = &usb_simtec_info; + int ret; - s3c2410_gpio_cfgpin(S3C2410_GPB4, S3C2410_GPB4_OUTP); - s3c2410_gpio_setpin(S3C2410_GPB4, 1); + printk("USB Power Control, (c) 2004 Simtec Electronics\n"); + + ret = gpio_request(S3C2410_GPB(4), "USB power control"); + if (ret < 0) { + pr_err("%s: failed to get GPB4\n", __func__); + return ret; + } + + ret = gpio_request(S3C2410_GPG(10), "USB overcurrent"); + if (ret < 0) { + pr_err("%s: failed to get GPG10\n", __func__); + gpio_free(S3C2410_GPB(4)); + return ret; + } + + /* turn power on */ + gpio_direction_output(S3C2410_GPB(4), 1); + gpio_direction_input(S3C2410_GPG(10)); + + s3c_device_usb.dev.platform_data = &usb_simtec_info; return 0; } diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig index ca99564ae4b5..63586ffd0ae7 100644 --- a/arch/arm/mach-s3c2412/Kconfig +++ b/arch/arm/mach-s3c2412/Kconfig @@ -38,6 +38,7 @@ menu "S3C2412 Machines" config MACH_JIVE bool "Logitech Jive" select CPU_S3C2412 + select S3C_DEV_USB_HOST help Say Y here if you are using the Logitech Jive. @@ -50,6 +51,7 @@ config MACH_SMDK2413 select CPU_S3C2412 select MACH_S3C2413 select MACH_SMDK + select S3C_DEV_USB_HOST help Say Y here if you are using an SMDK2413 @@ -72,6 +74,7 @@ config MACH_SMDK2412 config MACH_VSTMS bool "VMSTMS" select CPU_S3C2412 + select S3C_DEV_USB_HOST help Say Y here if you are using an VSTMS board diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c index 9e3478506c6f..f8d16fc10bc6 100644 --- a/arch/arm/mach-s3c2412/dma.c +++ b/arch/arm/mach-s3c2412/dma.c @@ -20,12 +20,13 @@ #include -#include +#include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index 8f0d37d43b43..8df506eac903 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -356,8 +357,8 @@ static void jive_lcm_reset(unsigned int set) { printk(KERN_DEBUG "%s(%d)\n", __func__, set); - s3c2410_gpio_setpin(S3C2410_GPG13, set); - s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPG(13), set); + s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT); } #undef LCD_UPPER_MARGIN @@ -390,13 +391,13 @@ static struct ili9320_platdata jive_lcm_config = { static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs) { - s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1); + s3c2410_gpio_setpin(S3C2410_GPB(7), cs ? 0 : 1); } static struct s3c2410_spigpio_info jive_lcd_spi = { .bus_num = 1, - .pin_clk = S3C2410_GPG8, - .pin_mosi = S3C2410_GPB8, + .pin_clk = S3C2410_GPG(8), + .pin_mosi = S3C2410_GPB(8), .num_chipselect = 1, .chip_select = jive_lcd_spi_chipselect, }; @@ -412,13 +413,13 @@ static struct platform_device jive_device_lcdspi = { static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs) { - s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1); + s3c2410_gpio_setpin(S3C2410_GPH(10), cs ? 0 : 1); } static struct s3c2410_spigpio_info jive_wm8750_spi = { .bus_num = 2, - .pin_clk = S3C2410_GPB4, - .pin_mosi = S3C2410_GPB9, + .pin_clk = S3C2410_GPB(4), + .pin_mosi = S3C2410_GPB(9), .num_chipselect = 1, .chip_select = jive_wm8750_chipselect, }; @@ -479,7 +480,7 @@ static struct platform_device *jive_devices[] __initdata = { }; static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = { - .vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */ + .vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */ }; /* Jive power management device */ @@ -529,8 +530,8 @@ static void jive_power_off(void) { printk(KERN_INFO "powering system down...\n"); - s3c2410_gpio_setpin(S3C2410_GPC5, 1); - s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPC(5), 1); + s3c2410_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT); } static void __init jive_machine_init(void) @@ -634,22 +635,22 @@ static void __init jive_machine_init(void) /* initialise the spi */ - s3c2410_gpio_setpin(S3C2410_GPG13, 0); - s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPG(13), 0); + s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPB7, 1); - s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPB(7), 1); + s3c2410_gpio_cfgpin(S3C2410_GPB(7), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPB6, 0); - s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPB(6), 0); + s3c2410_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT); - s3c2410_gpio_setpin(S3C2410_GPG8, 1); - s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPG(8), 1); + s3c2410_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT); /* initialise the WM8750 spi */ - s3c2410_gpio_setpin(S3C2410_GPH10, 1); - s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPH(10), 1); + s3c2410_gpio_cfgpin(S3C2410_GPH(10), S3C2410_GPIO_OUTPUT); /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index eba66aa6bd20..9a5e43419722 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -84,10 +85,10 @@ static void smdk2413_udc_pullup(enum s3c2410_udc_cmd_e cmd) switch (cmd) { case S3C2410_UDC_P_ENABLE : - s3c2410_gpio_setpin(S3C2410_GPF2, 1); + s3c2410_gpio_setpin(S3C2410_GPF(2), 1); break; case S3C2410_UDC_P_DISABLE : - s3c2410_gpio_setpin(S3C2410_GPF2, 0); + s3c2410_gpio_setpin(S3C2410_GPF(2), 0); break; case S3C2410_UDC_P_RESET : break; @@ -134,8 +135,8 @@ static void __init smdk2413_machine_init(void) { /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ - s3c2410_gpio_setpin(S3C2410_GPF2, 0); - s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPF(2), 0); + s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | S3C2410_MISCCR_USBSUSPND0 | diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index cde5ae9a4340..5df73cbf2b40 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig @@ -33,6 +33,7 @@ config MACH_ANUBIS select PM_SIMTEC if PM select HAVE_PATA_PLATFORM select S3C24XX_GPIO_EXTRA64 + select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec Electronics ANUBIS development system @@ -43,6 +44,7 @@ config MACH_OSIRIS select S3C24XX_DCLK select PM_SIMTEC if PM select S3C24XX_GPIO_EXTRA128 + select S3C_DEV_USB_HOST help Say Y here if you are using the Simtec IM2440D20 module, also known as the Osiris. @@ -58,12 +60,14 @@ config ARCH_S3C2440 bool "SMDK2440" select CPU_S3C2440 select MACH_SMDK + select S3C_DEV_USB_HOST help Say Y here if you are using the SMDK2440. config MACH_NEXCODER_2440 bool "NexVision NEXCODER 2440 Light Board" select CPU_S3C2440 + select S3C_DEV_USB_HOST help Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board @@ -76,6 +80,7 @@ config SMDK2440_CPU2440 config MACH_AT2440EVB bool "Avantech AT2440EVB development board" select CPU_S3C2440 + select S3C_DEV_USB_HOST help Say Y here if you are using the AT2440EVB development board diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c index 69b6cf34df47..e08e081430f0 100644 --- a/arch/arm/mach-s3c2440/dma.c +++ b/arch/arm/mach-s3c2440/dma.c @@ -17,14 +17,16 @@ #include #include +#include #include -#include +#include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 9c6abf9fb540..68f3870991bf 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -468,7 +469,7 @@ static void __init anubis_map_io(void) anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large); } else { /* ensure that the GPIO is setup */ - s3c2410_gpio_setpin(S3C2410_GPA0, 1); + s3c2410_gpio_setpin(S3C2410_GPA(0), 1); } } diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index 315c42e31278..dfc7010935da 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -166,7 +166,7 @@ static struct platform_device at2440evb_device_eth = { }; static struct s3c24xx_mci_pdata at2440evb_mci_pdata = { - .gpio_detect = S3C2410_GPG10, + .gpio_detect = S3C2410_GPG(10), }; /* 7" LCD panel */ diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c index 7aeaa972d7f5..d43edede590e 100644 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -120,16 +121,16 @@ static struct platform_device *nexcoder_devices[] __initdata = { static void __init nexcoder_sensorboard_init(void) { // Initialize SCCB bus - s3c2410_gpio_setpin(S3C2410_GPE14, 1); // IICSCL - s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_OUTP); - s3c2410_gpio_setpin(S3C2410_GPE15, 1); // IICSDA - s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_OUTP); + s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL + s3c2410_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT); + s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA + s3c2410_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT); // Power up the sensor board - s3c2410_gpio_setpin(S3C2410_GPF1, 1); - s3c2410_gpio_cfgpin(S3C2410_GPF1, S3C2410_GPF1_OUTP); // CAM_GPIO7 => nLDO_PWRDN - s3c2410_gpio_setpin(S3C2410_GPF2, 0); - s3c2410_gpio_cfgpin(S3C2410_GPF2, S3C2410_GPF2_OUTP); // CAM_GPIO6 => CAM_PWRDN + s3c2410_gpio_setpin(S3C2410_GPF(1), 1); + s3c2410_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN + s3c2410_gpio_setpin(S3C2410_GPF(2), 0); + s3c2410_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN } static void __init nexcoder_map_io(void) diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index c8a46685ce38..cba064b49a64 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -291,8 +292,8 @@ static int osiris_pm_suspend(struct sys_device *sd, pm_message_t state) __raw_writeb(tmp, OSIRIS_VA_CTRL0); /* ensure that an nRESET is not generated on resume. */ - s3c2410_gpio_setpin(S3C2410_GPA21, 1); - s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT); + s3c2410_gpio_setpin(S3C2410_GPA(21), 1); + s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT); return 0; } @@ -304,7 +305,7 @@ static int osiris_pm_resume(struct sys_device *sd) __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0); - s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT); + s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT); return 0; } @@ -384,7 +385,7 @@ static void __init osiris_map_io(void) osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large); } else { /* write-protect line to the NAND */ - s3c2410_gpio_setpin(S3C2410_GPA0, 1); + s3c2410_gpio_setpin(S3C2410_GPA(0), 1); } /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */ diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c index 8430e5829186..397f3b5c0b47 100644 --- a/arch/arm/mach-s3c2443/dma.c +++ b/arch/arm/mach-s3c2443/dma.c @@ -20,12 +20,13 @@ #include -#include +#include #include #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-s3c6400/Kconfig b/arch/arm/mach-s3c6400/Kconfig index 6da82b5c09ba..f5af212066c3 100644 --- a/arch/arm/mach-s3c6400/Kconfig +++ b/arch/arm/mach-s3c6400/Kconfig @@ -5,4 +5,27 @@ # # Licensed under GPLv2 -# Currently nothing here, this will be added later +# Configuration options for the S3C6410 CPU + +config CPU_S3C6400 + bool + select CPU_S3C6400_INIT + select CPU_S3C6400_CLOCK + help + Enable S3C6400 CPU support + +config S3C6400_SETUP_SDHCI + bool + help + Internal configuration for default SDHCI + setup for S3C6400. + +# S36400 Macchine support + +config MACH_SMDK6400 + bool "SMDK6400" + select CPU_S3C6400 + select S3C_DEV_HSMMC + select S3C6400_SETUP_SDHCI + help + Machine support for the Samsung SMDK6400 diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile index 8f397db25b87..df1ce4aa03e5 100644 --- a/arch/arm/mach-s3c6400/Makefile +++ b/arch/arm/mach-s3c6400/Makefile @@ -12,4 +12,12 @@ obj- := # Core support for S3C6400 system -obj-n += blank.o +obj-$(CONFIG_CPU_S3C6400) += s3c6400.o + +# setup support + +obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o + +# Machine support + +obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h index 9771ac2cb07e..1067619f0ba0 100644 --- a/arch/arm/mach-s3c6400/include/mach/dma.h +++ b/arch/arm/mach-s3c6400/include/mach/dma.h @@ -11,6 +11,63 @@ #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H __FILE__ -/* currently nothing here, placeholder */ +#define S3C_DMA_CHANNELS (16) + +/* see mach-s3c2410/dma.h for notes on dma channel numbers */ + +/* Note, for the S3C64XX architecture we keep the DMACH_ + * defines in the order they are allocated to [S]DMA0/[S]DMA1 + * so that is easy to do DHACH_ -> DMA controller conversion + */ +enum dma_ch { + /* DMA0/SDMA0 */ + DMACH_UART0 = 0, + DMACH_UART0_SRC2, + DMACH_UART1, + DMACH_UART1_SRC2, + DMACH_UART2, + DMACH_UART2_SRC2, + DMACH_UART3, + DMACH_UART3_SRC2, + DMACH_PCM0_TX, + DMACH_PCM0_RX, + DMACH_I2S0_OUT, + DMACH_I2S0_IN, + DMACH_SPI0_TX, + DMACH_SPI0_RX, + DMACH_HSI_I2SV40_TX, + DMACH_HSI_I2SV40_RX, + + /* DMA1/SDMA1 */ + DMACH_PCM1_TX = 16, + DMACH_PCM1_RX, + DMACH_I2S1_OUT, + DMACH_I2S1_IN, + DMACH_SPI1_TX, + DMACH_SPI1_RX, + DMACH_AC97_PCMOUT, + DMACH_AC97_PCMIN, + DMACH_AC97_MICIN, + DMACH_PWM, + DMACH_IRDA, + DMACH_EXTERNAL, + DMACH_RES1, + DMACH_RES2, + DMACH_SECURITY_RX, /* SDMA1 only */ + DMACH_SECURITY_TX, /* SDMA1 only */ + DMACH_MAX /* the end */ +}; + +static __inline__ int s3c_dma_has_circular(void) +{ + /* we will be supporting ciruclar buffers as soon as we have DMA + * engine support. + */ + return 1; +} + +#define S3C2410_DMAF_CIRCULAR (1 << 0) + +#include #endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index 8199972ed5bd..5057d9948d35 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -39,6 +39,8 @@ #define S3C_VA_UART3 S3C_VA_UARTx(3) #define S3C64XX_PA_FB (0x77100000) +#define S3C64XX_PA_USB_HSOTG (0x7C000000) +#define S3C64XX_PA_WATCHDOG (0x7E004000) #define S3C64XX_PA_SYSCON (0x7E00F000) #define S3C64XX_PA_IIS0 (0x7F002000) #define S3C64XX_PA_IIS1 (0x7F003000) @@ -57,6 +59,8 @@ #define S3C64XX_PA_MODEM (0x74108000) #define S3C64XX_VA_MODEM S3C_ADDR(0x00600000) +#define S3C64XX_PA_USBHOST (0x74300000) + /* place VICs close together */ #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) @@ -69,5 +73,7 @@ #define S3C_PA_IIC S3C64XX_PA_IIC0 #define S3C_PA_IIC1 S3C64XX_PA_IIC1 #define S3C_PA_FB S3C64XX_PA_FB +#define S3C_PA_USBHOST S3C64XX_PA_USBHOST +#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG #endif /* __ASM_ARCH_6400_MAP_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/regs-clock.h b/arch/arm/mach-s3c6400/include/mach/regs-clock.h new file mode 100644 index 000000000000..a6c7f4eb3a1b --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/regs-clock.h @@ -0,0 +1,16 @@ +/* linux/arch/arm/mach-s3c6400/include/mach/regs-clock.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C64XX - clock register compatibility with s3c24xx + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h index 090cfd969bc7..2e58cb7a7147 100644 --- a/arch/arm/mach-s3c6400/include/mach/system.h +++ b/arch/arm/mach-s3c6400/include/mach/system.h @@ -11,6 +11,8 @@ #ifndef __ASM_ARCH_SYSTEM_H #define __ASM_ARCH_SYSTEM_H __FILE__ +#include + static void arch_idle(void) { /* nothing here yet */ @@ -18,7 +20,11 @@ static void arch_idle(void) static void arch_reset(char mode, const char *cmd) { - /* nothing here yet */ + if (mode != 's') + arch_wdt_reset(); + + /* if all else fails, or mode was for soft, jump to 0 */ + cpu_reset(0); } #endif /* __ASM_ARCH_IRQ_H */ diff --git a/arch/arm/mach-s3c6400/mach-smdk6400.c b/arch/arm/mach-s3c6400/mach-smdk6400.c new file mode 100644 index 000000000000..ab19285389a7 --- /dev/null +++ b/arch/arm/mach-s3c6400/mach-smdk6400.c @@ -0,0 +1,96 @@ +/* linux/arch/arm/mach-s3c6400/mach-smdk6400.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include +#include + +#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK +#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB +#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE + +static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = 0x3c5, + .ulcon = 0x03, + .ufcon = 0x51, + }, +}; + +static struct map_desc smdk6400_iodesc[] = {}; + +static void __init smdk6400_map_io(void) +{ + s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc)); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs)); +} + +static struct platform_device *smdk6400_devices[] __initdata = { + &s3c_device_hsmmc1, + &s3c_device_i2c0, +}; + +static struct i2c_board_info i2c_devs[] __initdata = { + { I2C_BOARD_INFO("wm8753", 0x1A), }, + { I2C_BOARD_INFO("24c08", 0x50), }, +}; + +static void __init smdk6400_machine_init(void) +{ + i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs)); + platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices)); +} + +MACHINE_START(SMDK6400, "SMDK6400") + /* Maintainer: Ben Dooks */ + .phys_io = S3C_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, + .boot_params = S3C64XX_PA_SDRAM + 0x100, + + .init_irq = s3c6400_init_irq, + .map_io = smdk6400_map_io, + .init_machine = smdk6400_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c new file mode 100644 index 000000000000..1ece887d90bb --- /dev/null +++ b/arch/arm/mach-s3c6400/s3c6400.c @@ -0,0 +1,89 @@ +/* linux/arch/arm/mach-s3c6410/cpu.c + * + * Copyright 2009 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +void __init s3c6400_map_io(void) +{ + /* setup SDHCI */ + + s3c6400_default_sdhci0(); + s3c6400_default_sdhci1(); + + /* the i2c devices are directly compatible with s3c2440 */ + s3c_i2c0_setname("s3c2440-i2c"); +} + +void __init s3c6400_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initialising clocks\n", __func__); + s3c24xx_register_baseclocks(xtal); + s3c64xx_register_clocks(); + s3c6400_register_clocks(S3C6400_CLKDIV0_ARM_MASK); + s3c6400_setup_clocks(); +} + +void __init s3c6400_init_irq(void) +{ + /* VIC0 does not have IRQS 5..7, + * VIC1 is fully populated. */ + s3c64xx_init_irq(~0 & ~(0xf << 5), ~0); +} + +struct sysdev_class s3c6400_sysclass = { + .name = "s3c6400-core", +}; + +static struct sys_device s3c6400_sysdev = { + .cls = &s3c6400_sysclass, +}; + +static int __init s3c6400_core_init(void) +{ + return sysdev_class_register(&s3c6400_sysclass); +} + +core_initcall(s3c6400_core_init); + +int __init s3c6400_init(void) +{ + printk("S3C6400: Initialising architecture\n"); + + return sysdev_register(&s3c6400_sysdev); +} diff --git a/arch/arm/mach-s3c6400/setup-sdhci.c b/arch/arm/mach-s3c6400/setup-sdhci.c new file mode 100644 index 000000000000..b93dafbee1f4 --- /dev/null +++ b/arch/arm/mach-s3c6400/setup-sdhci.c @@ -0,0 +1,63 @@ +/* linux/arch/arm/mach-s3c6410/setup-sdhci.c + * + * Copyright 2008 Simtec Electronics + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ + +char *s3c6400_hsmmc_clksrcs[4] = { + [0] = "hsmmc", + [1] = "hsmmc", + [2] = "mmc_bus", + /* [3] = "48m", - note not succesfully used yet */ +}; + +void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev, + void __iomem *r, + struct mmc_ios *ios, + struct mmc_card *card) +{ + u32 ctrl2, ctrl3; + + ctrl2 = readl(r + S3C_SDHCI_CONTROL2); + ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; + ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | + S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | + S3C_SDHCI_CTRL2_ENFBCLKRX | + S3C_SDHCI_CTRL2_DFCNT_NONE | + S3C_SDHCI_CTRL2_ENCLKOUTHOLD); + + if (ios->clock < 25 * 1000000) + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | + S3C_SDHCI_CTRL3_FCSEL2 | + S3C_SDHCI_CTRL3_FCSEL1 | + S3C_SDHCI_CTRL3_FCSEL0); + else + ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); + + printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); + writel(ctrl2, r + S3C_SDHCI_CONTROL2); + writel(ctrl3, r + S3C_SDHCI_CONTROL3); +} + diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig index 1d5010070027..e63aac7f4e5a 100644 --- a/arch/arm/mach-s3c6410/Kconfig +++ b/arch/arm/mach-s3c6410/Kconfig @@ -16,9 +16,18 @@ config CPU_S3C6410 config S3C6410_SETUP_SDHCI bool + select S3C64XX_SETUP_SDHCI_GPIO help Internal helper functions for S3C6410 based SDHCI systems +config MACH_ANW6410 + bool "A&W6410" + select CPU_S3C6410 + select S3C_DEV_FB + select S3C64XX_SETUP_FB_24BPP + help + Machine support for the A&W6410 + config MACH_SMDK6410 bool "SMDK6410" select CPU_S3C6410 @@ -26,6 +35,8 @@ config MACH_SMDK6410 select S3C_DEV_HSMMC1 select S3C_DEV_I2C1 select S3C_DEV_FB + select S3C_DEV_USB_HOST + select S3C_DEV_USB_HSOTG select S3C6410_SETUP_SDHCI select S3C64XX_SETUP_I2C1 select S3C64XX_SETUP_FB_24BPP @@ -60,3 +71,29 @@ config SMDK6410_SD_CH1 channels 0 and 1 are the same. endchoice + +config SMDK6410_WM1190_EV1 + bool "Support Wolfson Microelectronics 1190-EV1 PMIC card" + depends on MACH_SMDK6410 + select REGULATOR + select REGULATOR_WM8350 + select MFD_WM8350_I2C + select MFD_WM8350_CONFIG_MODE_0 + select MFD_WM8350_CONFIG_MODE_3 + select MFD_WM8352_CONFIG_MODE_0 + help + The Wolfson Microelectronics 1190-EV1 is a WM835x based PMIC + and audio daughtercard for the Samsung SMDK6410 reference + platform. Enabling this option will build support for this + module into the kernel. The presence of the module will be + detected at runtime so the the resulting kernel can be used + with or without the 1190-EV1 fitted. + +config MACH_NCP + bool "NCP" + select CPU_S3C6410 + select S3C_DEV_I2C1 + select S3C_DEV_HSMMC1 + select S3C64XX_SETUP_I2C1 + help + Machine support for the Samsung NCP diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile index 2cd4f189036b..6f9deac88612 100644 --- a/arch/arm/mach-s3c6410/Makefile +++ b/arch/arm/mach-s3c6410/Makefile @@ -20,4 +20,8 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o # machine support +obj-$(CONFIG_MACH_ANW6410) += mach-anw6410.o obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o +obj-$(CONFIG_MACH_NCP) += mach-ncp.o + + diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c index 6a73ca6b7a3a..ade904de8895 100644 --- a/arch/arm/mach-s3c6410/cpu.c +++ b/arch/arm/mach-s3c6410/cpu.c @@ -31,6 +31,7 @@ #include #include +#include #include #include @@ -68,7 +69,7 @@ void __init s3c6410_init_clocks(int xtal) printk(KERN_DEBUG "%s: initialising clocks\n", __func__); s3c24xx_register_baseclocks(xtal); s3c64xx_register_clocks(); - s3c6400_register_clocks(); + s3c6400_register_clocks(S3C6410_CLKDIV0_ARM_MASK); s3c6400_setup_clocks(); } diff --git a/arch/arm/mach-s3c6410/mach-anw6410.c b/arch/arm/mach-s3c6410/mach-anw6410.c new file mode 100644 index 000000000000..661cca63de25 --- /dev/null +++ b/arch/arm/mach-s3c6410/mach-anw6410.c @@ -0,0 +1,245 @@ +/* linux/arch/arm/mach-s3c6410/mach-anw6410.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * Copyright 2009 Kwangwoo Lee + * Kwangwoo Lee + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include