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clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf,
chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching
Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL
for SD clock switching status.
Fixes: eaff33646f
("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-3-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
parent
d5252d9697
commit
549f4ae260
1 changed files with 10 additions and 7 deletions
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@ -188,7 +188,8 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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u32 off = GET_REG_OFFSET(hwdata->conf);
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u32 off = GET_REG_OFFSET(hwdata->conf);
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u32 shift = GET_SHIFT(hwdata->conf);
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u32 shift = GET_SHIFT(hwdata->conf);
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const u32 clk_src_266 = 2;
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const u32 clk_src_266 = 2;
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u32 bitmask;
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u32 msk, val, bitmask;
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int ret;
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/*
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/*
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* As per the HW manual, we should not directly switch from 533 MHz to
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* As per the HW manual, we should not directly switch from 533 MHz to
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@ -202,13 +203,9 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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* the index to value mapping is done by adding 1 to the index.
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* the index to value mapping is done by adding 1 to the index.
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*/
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*/
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bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
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bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
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if (index != clk_src_266) {
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u32 msk, val;
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int ret;
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writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
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msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
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msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
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if (index != clk_src_266) {
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writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
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ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
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ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
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!(val & msk), 100,
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!(val & msk), 100,
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@ -221,7 +218,13 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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writel(bitmask | ((index + 1) << shift), priv->base + off);
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writel(bitmask | ((index + 1) << shift), priv->base + off);
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return 0;
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ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
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!(val & msk), 100,
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CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
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if (ret)
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dev_err(priv->dev, "failed to switch clk source\n");
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return ret;
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}
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}
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static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
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static u8 rzg2l_cpg_sd_clk_mux_get_parent(struct clk_hw *hw)
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