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staging: sm750fb: rename PANEL_PLL_CTRL_* fields to PLL_CTRL_*

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Several PLL control registers have the same layout and therefore the
field definitions may be shared for those registers. Renaming
definitions of PANEL_PLL_CTRL_* fields to more generic PLL_CTRL_* will
allow reusing these definitions for other PLL control registers.

Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mike Rapoport 2016-02-10 18:33:55 +02:00 committed by Greg Kroah-Hartman
parent 0c4d85fc7f
commit 54feb93153
3 changed files with 27 additions and 27 deletions
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22
drivers/staging/sm750fb/ddk750_chip.c
View file

@ -36,10 +36,10 @@ static unsigned int get_mxclk_freq(void)
return MHz(130);
pll_reg = PEEK32(MXCLK_PLL_CTRL);
M = FIELD_GET(pll_reg, PANEL_PLL_CTRL, M);
N = FIELD_GET(pll_reg, PANEL_PLL_CTRL, N);
OD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, OD);
POD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, POD);
M = FIELD_GET(pll_reg, PLL_CTRL, M);
N = FIELD_GET(pll_reg, PLL_CTRL, N);
OD = FIELD_GET(pll_reg, PLL_CTRL, OD);
POD = FIELD_GET(pll_reg, PLL_CTRL, POD);
return DEFAULT_INPUT_CLOCK * M / N / (1 << OD) / (1 << POD);
}
@ -364,15 +364,15 @@ unsigned int formatPllReg(pll_value_t *pPLL)
* applied to any PLL in the calling function.
*/
reg =
FIELD_SET(0, PANEL_PLL_CTRL, BYPASS, OFF)
| FIELD_SET(0, PANEL_PLL_CTRL, POWER, ON)
| FIELD_SET(0, PANEL_PLL_CTRL, INPUT, OSC)
FIELD_SET(0, PLL_CTRL, BYPASS, OFF)
| FIELD_SET(0, PLL_CTRL, POWER, ON)
| FIELD_SET(0, PLL_CTRL, INPUT, OSC)
#ifndef VALIDATION_CHIP
| FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD)
| FIELD_VALUE(0, PLL_CTRL, POD, pPLL->POD)
#endif
| FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD)
| FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N)
| FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M);
| FIELD_VALUE(0, PLL_CTRL, OD, pPLL->OD)
| FIELD_VALUE(0, PLL_CTRL, N, pPLL->N)
| FIELD_VALUE(0, PLL_CTRL, M, pPLL->M);
return reg;
}

4
drivers/staging/sm750fb/ddk750_display.c
View file

@ -126,8 +126,8 @@ static void waitNextVerticalSync(int ctrl, int delay)
/* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */
if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==
PANEL_PLL_CTRL_POWER_OFF) ||
if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PLL_CTRL, POWER) ==
PLL_CTRL_POWER_OFF) ||
(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
return;

28
drivers/staging/sm750fb/ddk750_reg.h
View file

@ -517,23 +517,23 @@
#define PLL_CLK_COUNT_COUNTER 15:0
#define PANEL_PLL_CTRL 0x00005C
#define PANEL_PLL_CTRL_BYPASS 18:18
#define PANEL_PLL_CTRL_BYPASS_OFF 0
#define PANEL_PLL_CTRL_BYPASS_ON 1
#define PANEL_PLL_CTRL_POWER 17:17
#define PANEL_PLL_CTRL_POWER_OFF 0
#define PANEL_PLL_CTRL_POWER_ON 1
#define PANEL_PLL_CTRL_INPUT 16:16
#define PANEL_PLL_CTRL_INPUT_OSC 0
#define PANEL_PLL_CTRL_INPUT_TESTCLK 1
#define PLL_CTRL_BYPASS 18:18
#define PLL_CTRL_BYPASS_OFF 0
#define PLL_CTRL_BYPASS_ON 1
#define PLL_CTRL_POWER 17:17
#define PLL_CTRL_POWER_OFF 0
#define PLL_CTRL_POWER_ON 1
#define PLL_CTRL_INPUT 16:16
#define PLL_CTRL_INPUT_OSC 0
#define PLL_CTRL_INPUT_TESTCLK 1
#ifdef VALIDATION_CHIP
#define PANEL_PLL_CTRL_OD 15:14
#define PLL_CTRL_OD 15:14
#else
#define PANEL_PLL_CTRL_POD 15:14
#define PANEL_PLL_CTRL_OD 13:12
#define PLL_CTRL_POD 15:14
#define PLL_CTRL_OD 13:12
#endif
#define PANEL_PLL_CTRL_N 11:8
#define PANEL_PLL_CTRL_M 7:0
#define PLL_CTRL_N 11:8
#define PLL_CTRL_M 7:0
#define CRT_PLL_CTRL 0x000060
#define CRT_PLL_CTRL_BYPASS 18:18