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staging: sm750fb: rename PANEL_PLL_CTRL_* fields to PLL_CTRL_*
Several PLL control registers have the same layout and therefore the field definitions may be shared for those registers. Renaming definitions of PANEL_PLL_CTRL_* fields to more generic PLL_CTRL_* will allow reusing these definitions for other PLL control registers. Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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0c4d85fc7f
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54feb93153
3 changed files with 27 additions and 27 deletions
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@ -36,10 +36,10 @@ static unsigned int get_mxclk_freq(void)
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return MHz(130);
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pll_reg = PEEK32(MXCLK_PLL_CTRL);
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M = FIELD_GET(pll_reg, PANEL_PLL_CTRL, M);
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N = FIELD_GET(pll_reg, PANEL_PLL_CTRL, N);
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OD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, OD);
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POD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, POD);
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M = FIELD_GET(pll_reg, PLL_CTRL, M);
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N = FIELD_GET(pll_reg, PLL_CTRL, N);
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OD = FIELD_GET(pll_reg, PLL_CTRL, OD);
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POD = FIELD_GET(pll_reg, PLL_CTRL, POD);
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return DEFAULT_INPUT_CLOCK * M / N / (1 << OD) / (1 << POD);
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}
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@ -364,15 +364,15 @@ unsigned int formatPllReg(pll_value_t *pPLL)
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* applied to any PLL in the calling function.
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*/
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reg =
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FIELD_SET(0, PANEL_PLL_CTRL, BYPASS, OFF)
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| FIELD_SET(0, PANEL_PLL_CTRL, POWER, ON)
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| FIELD_SET(0, PANEL_PLL_CTRL, INPUT, OSC)
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FIELD_SET(0, PLL_CTRL, BYPASS, OFF)
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| FIELD_SET(0, PLL_CTRL, POWER, ON)
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| FIELD_SET(0, PLL_CTRL, INPUT, OSC)
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#ifndef VALIDATION_CHIP
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| FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD)
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| FIELD_VALUE(0, PLL_CTRL, POD, pPLL->POD)
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#endif
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| FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD)
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| FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N)
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| FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M);
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| FIELD_VALUE(0, PLL_CTRL, OD, pPLL->OD)
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| FIELD_VALUE(0, PLL_CTRL, N, pPLL->N)
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| FIELD_VALUE(0, PLL_CTRL, M, pPLL->M);
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return reg;
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}
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@ -126,8 +126,8 @@ static void waitNextVerticalSync(int ctrl, int delay)
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/* Do not wait when the Primary PLL is off or display control is already off.
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This will prevent the software to wait forever. */
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if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==
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PANEL_PLL_CTRL_POWER_OFF) ||
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if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PLL_CTRL, POWER) ==
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PLL_CTRL_POWER_OFF) ||
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(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
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PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
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return;
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@ -517,23 +517,23 @@
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#define PLL_CLK_COUNT_COUNTER 15:0
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#define PANEL_PLL_CTRL 0x00005C
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#define PANEL_PLL_CTRL_BYPASS 18:18
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#define PANEL_PLL_CTRL_BYPASS_OFF 0
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#define PANEL_PLL_CTRL_BYPASS_ON 1
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#define PANEL_PLL_CTRL_POWER 17:17
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#define PANEL_PLL_CTRL_POWER_OFF 0
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#define PANEL_PLL_CTRL_POWER_ON 1
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#define PANEL_PLL_CTRL_INPUT 16:16
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#define PANEL_PLL_CTRL_INPUT_OSC 0
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#define PANEL_PLL_CTRL_INPUT_TESTCLK 1
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#define PLL_CTRL_BYPASS 18:18
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#define PLL_CTRL_BYPASS_OFF 0
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#define PLL_CTRL_BYPASS_ON 1
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#define PLL_CTRL_POWER 17:17
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#define PLL_CTRL_POWER_OFF 0
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#define PLL_CTRL_POWER_ON 1
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#define PLL_CTRL_INPUT 16:16
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#define PLL_CTRL_INPUT_OSC 0
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#define PLL_CTRL_INPUT_TESTCLK 1
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#ifdef VALIDATION_CHIP
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#define PANEL_PLL_CTRL_OD 15:14
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#define PLL_CTRL_OD 15:14
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#else
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#define PANEL_PLL_CTRL_POD 15:14
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#define PANEL_PLL_CTRL_OD 13:12
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#define PLL_CTRL_POD 15:14
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#define PLL_CTRL_OD 13:12
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#endif
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#define PANEL_PLL_CTRL_N 11:8
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#define PANEL_PLL_CTRL_M 7:0
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#define PLL_CTRL_N 11:8
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#define PLL_CTRL_M 7:0
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#define CRT_PLL_CTRL 0x000060
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#define CRT_PLL_CTRL_BYPASS 18:18
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