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clk/samsung updates for 5.10
Minor refactoring removing most of the __clk_lookup() calls. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJfacm/AAoJEE1bIKeAnHqLIAwP/00F52a2Z9KSvQ2M/GDcE5HT 9GIJot/a/v4jZWZ0vw4B3rB1fW9U26/s6jApH5G7oB6Dtn3dFeaROcJMhMSWn0Rp zuvqFp0TFrq+M730qlDOwOS/5iso6d0Hu0tETXiXSrU3/YXJesMljxNqXANHd9wp HLHM6xRxQQc7fYShDan+wmV7KFx1s93UXa5HTjGsRqG+4oy1ENDvAZZphmjYj5JT PBf8dVWx6mBa5qyN2fyFppgFI0xhUdk9+QAcKkp1Ul7WBiRr5IRz7M5MuJ7pwabZ ofB8Rl7lUeDU3xrq/CoBiyerA1U0wNdsmJSU8QVJBWGqupT2QVUkm72k00zb+Ihj G5XW8EC1KODmVV4TKEpzIUTp+4rY/7IG2ZYS6CctJPcEMvyo7FbfdeIDpa+CtPCq oloQn2VFarfhsQNDbE8fVcbJzS9XAMFin4Ce5ZsQTmPn0iuOucyDqZuPreiGAcKO 1NznWmjFauQ5o5VCBI+of9o7F85yiH2pq/ALS3SDtPQCq3whYlZ2iBovKt7O5+4l V+/LgNQd4x9KF79UybywpnAxa6/sA+D1oQsz2TorUuEtQuKXF/85XBcBCfpwzqdO 4HcKwkuoe7obS1Avp+OlnyRgbvjItGx1KqjIcs5oAKzmHaV03LfbHlOW+qrBO99r tgs8iIYgYrcy1J79CBeo =Lu5d -----END PGP SIGNATURE----- Merge tag 'clk-v5.10-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: Minor refactoring removing most of the __clk_lookup() calls. * tag 'clk-v5.10-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Use cached clk_hws instead of __clk_lookup() calls clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions clk: samsung: Add clk ID definitions for the CPU parent clocks clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d clk: samsung: Keep top BPLL mux on Exynos542x enabled
This commit is contained in:
Stephen Boyd
commit
553be99d1f
9 changed files with 68 additions and 46 deletions
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@ -401,26 +401,34 @@ static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
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/* helper function to register a CPU clock */
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int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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unsigned int lookup_id, const char *name, const char *parent,
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const char *alt_parent, unsigned long offset,
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const struct exynos_cpuclk_cfg_data *cfg,
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unsigned int lookup_id, const char *name,
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const struct clk_hw *parent, const struct clk_hw *alt_parent,
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unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
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unsigned long num_cfgs, unsigned long flags)
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{
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struct exynos_cpuclk *cpuclk;
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struct clk_init_data init;
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struct clk *parent_clk;
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const char *parent_name;
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int ret = 0;
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if (IS_ERR(parent) || IS_ERR(alt_parent)) {
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pr_err("%s: invalid parent clock(s)\n", __func__);
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return -EINVAL;
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}
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cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
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if (!cpuclk)
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return -ENOMEM;
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parent_name = clk_hw_get_name(parent);
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init.name = name;
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init.flags = CLK_SET_RATE_PARENT;
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init.parent_names = &parent;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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init.ops = &exynos_cpuclk_clk_ops;
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cpuclk->alt_parent = alt_parent;
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cpuclk->hw.init = &init;
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cpuclk->ctrl_base = ctx->reg_base + offset;
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cpuclk->lock = &ctx->lock;
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@ -430,23 +438,8 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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else
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cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
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cpuclk->alt_parent = __clk_get_hw(__clk_lookup(alt_parent));
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if (!cpuclk->alt_parent) {
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pr_err("%s: could not lookup alternate parent %s\n",
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__func__, alt_parent);
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ret = -EINVAL;
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goto free_cpuclk;
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}
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parent_clk = __clk_lookup(parent);
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if (!parent_clk) {
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pr_err("%s: could not lookup parent clock %s\n",
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__func__, parent);
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ret = -EINVAL;
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goto free_cpuclk;
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}
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ret = clk_notifier_register(parent_clk, &cpuclk->clk_nb);
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ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
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if (ret) {
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pr_err("%s: failed to register clock notifier for %s\n",
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__func__, name);
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@ -471,7 +464,7 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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free_cpuclk_data:
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kfree(cpuclk->cfg);
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unregister_clk_nb:
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clk_notifier_unregister(parent_clk, &cpuclk->clk_nb);
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clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);
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free_cpuclk:
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kfree(cpuclk);
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return ret;
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@ -46,7 +46,7 @@ struct exynos_cpuclk_cfg_data {
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*/
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struct exynos_cpuclk {
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struct clk_hw hw;
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struct clk_hw *alt_parent;
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const struct clk_hw *alt_parent;
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void __iomem *ctrl_base;
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spinlock_t *lock;
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const struct exynos_cpuclk_cfg_data *cfg;
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@ -62,9 +62,9 @@ struct exynos_cpuclk {
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#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
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};
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extern int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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unsigned int lookup_id, const char *name,
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const char *parent, const char *alt_parent,
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const struct clk_hw *parent, const struct clk_hw *alt_parent,
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unsigned long offset,
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const struct exynos_cpuclk_cfg_data *cfg,
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unsigned long num_cfgs, unsigned long flags);
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@ -808,14 +808,16 @@ static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
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static void __init exynos3250_cmu_init(struct device_node *np)
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{
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struct samsung_clk_provider *ctx;
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struct clk_hw **hws;
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ctx = samsung_cmu_register_one(np, &cmu_info);
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if (!ctx)
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return;
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hws = ctx->clk_data.hws;
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p[0], mout_core_p[1], 0x14200,
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e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
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hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],
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0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
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CLK_CPU_HAS_DIV1);
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exynos3_core_down_clock(ctx->reg_base);
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@ -1233,6 +1233,8 @@ static void __init exynos4_clk_init(struct device_node *np,
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enum exynos4_soc soc)
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{
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struct samsung_clk_provider *ctx;
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struct clk_hw **hws;
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exynos4_soc = soc;
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reg_base = of_iomap(np, 0);
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@ -1240,6 +1242,7 @@ static void __init exynos4_clk_init(struct device_node *np,
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panic("%s: failed to map registers\n", __func__);
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ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
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hws = ctx->clk_data.hws;
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samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
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ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
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@ -1302,7 +1305,7 @@ static void __init exynos4_clk_init(struct device_node *np,
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exynos4210_fixed_factor_clks,
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ARRAY_SIZE(exynos4210_fixed_factor_clks));
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p4210[0], mout_core_p4210[1], 0x14200,
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hws[CLK_MOUT_APLL], hws[CLK_SCLK_MPLL], 0x14200,
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e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
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CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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} else {
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@ -1317,7 +1320,7 @@ static void __init exynos4_clk_init(struct device_node *np,
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ARRAY_SIZE(exynos4x12_fixed_factor_clks));
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
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hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C], 0x14200,
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e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
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CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
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}
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@ -253,14 +253,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
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/*
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* CMU_CPU
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*/
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MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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CLK_SET_RATE_PARENT, 0),
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MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
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/*
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* CMU_CORE
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*/
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MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
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MUX(CLK_MOUT_MPLL, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
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/*
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* CMU_TOP
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@ -782,6 +782,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
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{
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struct samsung_clk_provider *ctx;
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unsigned int tmp;
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struct clk_hw **hws;
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if (np) {
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reg_base = of_iomap(np, 0);
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@ -792,6 +793,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
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}
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ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
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hws = ctx->clk_data.hws;
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samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
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ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
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@ -821,7 +823,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
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samsung_clk_register_gate(ctx, exynos5250_gate_clks,
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ARRAY_SIZE(exynos5250_gate_clks));
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_cpu_p[0], mout_cpu_p[1], 0x200,
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hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL], 0x200,
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exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
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CLK_CPU_HAS_DIV1);
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@ -596,13 +596,14 @@ static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
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static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
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MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
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SRC_TOP7, 4, 1),
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MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
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MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
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MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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MUX(CLK_MOUT_MSPLL_KFC, "mout_mspll_kfc", mout_mspll_cpu_p,
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SRC_TOP7, 8, 2),
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MUX(CLK_MOUT_MSPLL_CPU, "mout_mspll_cpu", mout_mspll_cpu_p,
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SRC_TOP7, 12, 2),
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MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
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CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
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MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
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MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
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MUX_F(CLK_MOUT_KPLL, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
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CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
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MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
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@ -712,8 +713,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
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SRC_TOP12, 8, 1),
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MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
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SRC_TOP12, 12, 1),
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MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
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CLK_SET_RATE_PARENT, 0),
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MUX_F(CLK_MOUT_SW_ACLK_G3D, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p,
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SRC_TOP12, 16, 1, CLK_SET_RATE_PARENT, 0),
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MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
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SRC_TOP12, 20, 1),
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MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
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@ -1560,6 +1561,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
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enum exynos5x_soc soc)
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{
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struct samsung_clk_provider *ctx;
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struct clk_hw **hws;
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if (np) {
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reg_base = of_iomap(np, 0);
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@ -1572,6 +1574,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
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exynos5x_soc = soc;
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ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
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hws = ctx->clk_data.hws;
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samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
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ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
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@ -1623,15 +1626,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
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if (soc == EXYNOS5420) {
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_cpu_p[0], mout_cpu_p[1], 0x200,
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hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
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exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
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} else {
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exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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mout_cpu_p[0], mout_cpu_p[1], 0x200,
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hws[CLK_MOUT_APLL], hws[CLK_MOUT_MSPLL_CPU], 0x200,
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exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
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}
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exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
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mout_kfc_p[0], mout_kfc_p[1], 0x28200,
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hws[CLK_MOUT_KPLL], hws[CLK_MOUT_MSPLL_KFC], 0x28200,
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exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
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samsung_clk_extended_sleep_init(reg_base,
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@ -1654,7 +1657,12 @@ static void __init exynos5x_clk_init(struct device_node *np,
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* that the internal busses get their clock regardless of the
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* main G3D clock enablement status.
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*/
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clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
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clk_prepare_enable(hws[CLK_MOUT_SW_ACLK_G3D]->clk);
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/*
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* Keep top BPLL mux enabled permanently to ensure that DRAM operates
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* properly.
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*/
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clk_prepare_enable(hws[CLK_MOUT_BPLL]->clk);
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samsung_clk_of_add_provider(np, ctx);
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}
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@ -3679,6 +3679,7 @@ static void __init exynos5433_cmu_apollo_init(struct device_node *np)
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{
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void __iomem *reg_base;
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struct samsung_clk_provider *ctx;
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struct clk_hw **hws;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -3701,8 +3702,10 @@ static void __init exynos5433_cmu_apollo_init(struct device_node *np)
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samsung_clk_register_gate(ctx, apollo_gate_clks,
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ARRAY_SIZE(apollo_gate_clks));
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hws = ctx->clk_data.hws;
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exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
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mout_apollo_p[0], mout_apollo_p[1], 0x200,
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hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200,
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exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
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CLK_CPU_HAS_E5433_REGS_LAYOUT);
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@ -3933,6 +3936,7 @@ static void __init exynos5433_cmu_atlas_init(struct device_node *np)
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{
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void __iomem *reg_base;
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struct samsung_clk_provider *ctx;
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struct clk_hw **hws;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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@ -3955,8 +3959,10 @@ static void __init exynos5433_cmu_atlas_init(struct device_node *np)
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samsung_clk_register_gate(ctx, atlas_gate_clks,
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ARRAY_SIZE(atlas_gate_clks));
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hws = ctx->clk_data.hws;
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exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
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mout_atlas_p[0], mout_atlas_p[1], 0x200,
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||||
hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200,
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||||
exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
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||||
CLK_CPU_HAS_E5433_REGS_LAYOUT);
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||||
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||||
|
|
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|||
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|
@ -172,8 +172,10 @@
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#define CLK_MOUT_GPLL 1025
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#define CLK_MOUT_ACLK200_DISP1_SUB 1026
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||||
#define CLK_MOUT_ACLK300_DISP1_SUB 1027
|
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#define CLK_MOUT_APLL 1028
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#define CLK_MOUT_MPLL 1029
|
||||
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||||
/* must be greater than maximal clock id */
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||||
#define CLK_NR_CLKS 1028
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||||
#define CLK_NR_CLKS 1030
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
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|
|
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|
@ -230,6 +230,12 @@
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#define CLK_MOUT_USER_MAU_EPLL 659
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#define CLK_MOUT_SCLK_SPLL 660
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#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
|
||||
#define CLK_MOUT_SW_ACLK_G3D 662
|
||||
#define CLK_MOUT_APLL 663
|
||||
#define CLK_MOUT_MSPLL_CPU 664
|
||||
#define CLK_MOUT_KPLL 665
|
||||
#define CLK_MOUT_MSPLL_KFC 666
|
||||
|
||||
|
||||
/* divider clocks */
|
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#define CLK_DOUT_PIXEL 768
|
||||
|
|
|
|||
Loading…
Reference in a new issue