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mmc: sh_mmcif: Add support for eMMC Dual Data Rate
Some MMCIF implementations support the Dual Data Rate. With this patch, platforms can set the MMC_CAP_UHS_DDR50 capability flag in MMCIF platform data. This will let the MMC core to actually use the DDR mode. Signed-off-by: Teppei Kamijou <teppei.kamijou.yb@renesas.com> Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
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1 changed files with 14 additions and 0 deletions
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@ -88,6 +88,7 @@
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#define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
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#define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
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#define CMD_SET_CCSH (1 << 5)
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#define CMD_SET_DARS (1 << 2) /* Dual Data Rate */
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#define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
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#define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
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#define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
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@ -216,6 +217,7 @@ struct sh_mmcif_host {
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struct clk *hclk;
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unsigned int clk;
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int bus_width;
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unsigned char timing;
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bool sd_error;
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bool dying;
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long timeout;
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@ -781,6 +783,17 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
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dev_err(&host->pd->dev, "Unsupported bus width.\n");
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break;
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}
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switch (host->timing) {
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case MMC_TIMING_UHS_DDR50:
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/*
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* MMC core will only set this timing, if the host
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* advertises the MMC_CAP_UHS_DDR50 capability. MMCIF
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* implementations with this capability, e.g. sh73a0,
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* will have to set it in their platform data.
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*/
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tmp |= CMD_SET_DARS;
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break;
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}
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}
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/* DWEN */
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if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
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@ -1002,6 +1015,7 @@ static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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sh_mmcif_clock_control(host, ios->clock);
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}
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host->timing = ios->timing;
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host->bus_width = ios->bus_width;
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host->state = STATE_IDLE;
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}
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