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drm/i915: Split intel_read_wm_latency() into per-platform versions
No reaon to have this humongous if ladder in intel_read_wm_latency(). Just split it into nicer per-platforms functions. Also do the s/dev_priv/i915/ while touching all of this code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220908191646.20239-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä
parent
e2a5c05de6
commit
55544b2811
1 changed files with 104 additions and 85 deletions
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@ -2906,97 +2906,107 @@ adjust_wm_latency(struct drm_i915_private *i915,
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wm[0] += 1;
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}
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static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
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u16 wm[])
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static void mtl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
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{
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struct intel_uncore *uncore = &dev_priv->uncore;
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int max_level = ilk_wm_max_level(dev_priv);
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struct intel_uncore *uncore = &i915->uncore;
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int max_level = ilk_wm_max_level(i915);
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u32 val;
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if (DISPLAY_VER(dev_priv) >= 14) {
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u32 val;
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val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1);
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wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
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wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
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val = intel_uncore_read(uncore, MTL_LATENCY_LP0_LP1);
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wm[0] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
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wm[1] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
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val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3);
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wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
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wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
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val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5);
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wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
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wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
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val = intel_uncore_read(uncore, MTL_LATENCY_LP2_LP3);
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wm[2] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
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wm[3] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
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adjust_wm_latency(dev_priv, wm, max_level, 6);
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} else if (DISPLAY_VER(dev_priv) >= 9) {
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int read_latency = DISPLAY_VER(dev_priv) >= 12 ? 3 : 2;
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int mult = IS_DG2(dev_priv) ? 2 : 1;
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u32 val;
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int ret;
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val = intel_uncore_read(uncore, MTL_LATENCY_LP4_LP5);
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wm[4] = REG_FIELD_GET(MTL_LATENCY_LEVEL_EVEN_MASK, val);
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wm[5] = REG_FIELD_GET(MTL_LATENCY_LEVEL_ODD_MASK, val);
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/* read the first set of memory latencies[0:3] */
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val = 0; /* data0 to be programmed to 0 for first set */
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ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
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&val, NULL);
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adjust_wm_latency(i915, wm, max_level, 6);
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}
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if (ret) {
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drm_err(&dev_priv->drm,
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"SKL Mailbox read error = %d\n", ret);
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return;
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}
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static void skl_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
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{
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int max_level = ilk_wm_max_level(i915);
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int read_latency = DISPLAY_VER(i915) >= 12 ? 3 : 2;
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int mult = IS_DG2(i915) ? 2 : 1;
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u32 val;
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int ret;
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wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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/* read the second set of memory latencies[4:7] */
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val = 1; /* data0 to be programmed to 1 for second set */
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ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
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&val, NULL);
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if (ret) {
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drm_err(&dev_priv->drm,
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"SKL Mailbox read error = %d\n", ret);
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return;
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}
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wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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adjust_wm_latency(dev_priv, wm, max_level, read_latency);
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} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
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wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
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if (wm[0] == 0)
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wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);
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wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);
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wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);
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wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);
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wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
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} else if (DISPLAY_VER(dev_priv) >= 6) {
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u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
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wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
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wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
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wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);
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wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
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} else if (DISPLAY_VER(dev_priv) >= 5) {
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u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
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/* ILK primary LP0 latency is 700 ns */
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wm[0] = 7;
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wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);
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wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);
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} else {
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MISSING_CASE(INTEL_DEVID(dev_priv));
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/* read the first set of memory latencies[0:3] */
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val = 0; /* data0 to be programmed to 0 for first set */
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ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
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if (ret) {
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drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret);
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return;
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}
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wm[0] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[1] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[2] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[3] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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/* read the second set of memory latencies[4:7] */
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val = 1; /* data0 to be programmed to 1 for second set */
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ret = snb_pcode_read(&i915->uncore, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
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if (ret) {
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drm_err(&i915->drm, "SKL Mailbox read error = %d\n", ret);
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return;
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}
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wm[4] = (val & GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[5] = ((val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[6] = ((val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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wm[7] = ((val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
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GEN9_MEM_LATENCY_LEVEL_MASK) * mult;
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adjust_wm_latency(i915, wm, max_level, read_latency);
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}
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static void hsw_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
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{
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u64 sskpd;
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sskpd = intel_uncore_read64(&i915->uncore, MCH_SSKPD);
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wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
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if (wm[0] == 0)
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wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);
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wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);
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wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);
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wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);
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wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
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}
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static void snb_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
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{
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u32 sskpd;
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sskpd = intel_uncore_read(&i915->uncore, MCH_SSKPD);
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wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
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wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
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wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);
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wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
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}
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static void ilk_read_wm_latency(struct drm_i915_private *i915, u16 wm[])
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{
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u32 mltr;
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mltr = intel_uncore_read(&i915->uncore, MLTR_ILK);
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/* ILK primary LP0 latency is 700 ns */
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wm[0] = 7;
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wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);
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wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);
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}
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static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
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@ -3129,7 +3139,12 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
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static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
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{
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intel_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
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if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
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hsw_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
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else if (DISPLAY_VER(dev_priv) >= 6)
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snb_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
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else
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ilk_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
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memcpy(dev_priv->display.wm.spr_latency, dev_priv->display.wm.pri_latency,
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sizeof(dev_priv->display.wm.pri_latency));
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@ -3151,7 +3166,11 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
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static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
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{
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intel_read_wm_latency(dev_priv, dev_priv->display.wm.skl_latency);
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if (DISPLAY_VER(dev_priv) >= 14)
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mtl_read_wm_latency(dev_priv, dev_priv->display.wm.skl_latency);
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else
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skl_read_wm_latency(dev_priv, dev_priv->display.wm.skl_latency);
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intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->display.wm.skl_latency);
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}
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