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staging: sm750fb: remove unused calcPllValue2 function
The calcPllValue2 function is never called and therefore it can be removed. Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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2 changed files with 0 additions and 101 deletions
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@ -430,106 +430,6 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll)
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return ret;
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}
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unsigned int calcPllValue2(
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unsigned int ulRequestClk, /* Required pixel clock in Hz unit */
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pll_value_t *pPLL /* Structure to hold the value to be set in PLL */
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)
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{
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unsigned int M, N, OD, POD = 0, diff, pllClk, odPower, podPower;
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unsigned int bestDiff = 0xffffffff; /* biggest 32 bit unsigned number */
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unsigned int ret;
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/* Init PLL structure to know states */
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pPLL->M = 0;
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pPLL->N = 0;
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pPLL->OD = 0;
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pPLL->POD = 0;
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/* Sanity check: None at the moment */
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/* Convert everything in Khz range in order to avoid calculation overflow */
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pPLL->inputFreq /= 1000;
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ulRequestClk /= 1000;
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#ifndef VALIDATION_CHIP
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/* The maximum of post divider is 8. */
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for (POD = 0; POD <= 3; POD++)
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#endif
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{
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#ifndef VALIDATION_CHIP
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/* MXCLK_PLL does not have post divider. */
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if ((POD > 0) && (pPLL->clockType == MXCLK_PLL))
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break;
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#endif
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/* Work out 2 to the power of POD */
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podPower = 1 << POD;
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/* OD has only 2 bits [15:14] and its value must between 0 to 3 */
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for (OD = 0; OD <= 3; OD++) {
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/* Work out 2 to the power of OD */
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odPower = 1 << OD;
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#ifdef VALIDATION_CHIP
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if (odPower > 4)
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podPower = 4;
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else
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podPower = odPower;
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#endif
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/* N has 4 bits [11:8] and its value must between 2 and 15.
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The N == 1 will behave differently --> Result is not correct. */
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for (N = 2; N <= 15; N++) {
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/* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD)
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In the following steps, we try to work out a best M value given the others are known.
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To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy.
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*/
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M = ulRequestClk * N * odPower * 1000 / pPLL->inputFreq;
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M = roundedDiv(M, 1000);
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/* M field has only 8 bits, reject value bigger than 8 bits */
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if (M < 256) {
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/* Calculate the actual clock for a given M & N */
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pllClk = pPLL->inputFreq * M / N / odPower / podPower;
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/* How much are we different from the requirement */
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diff = absDiff(pllClk, ulRequestClk);
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if (diff < bestDiff) {
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bestDiff = diff;
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/* Store M and N values */
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pPLL->M = M;
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pPLL->N = N;
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pPLL->OD = OD;
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#ifdef VALIDATION_CHIP
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if (OD > 2)
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POD = 2;
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else
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POD = OD;
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#endif
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pPLL->POD = POD;
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}
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}
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}
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}
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}
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/* Restore input frequency from Khz to hz unit */
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ulRequestClk *= 1000;
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pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */
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/* Return actual frequency that the PLL can set */
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ret = calcPLL(pPLL);
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return ret;
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}
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unsigned int formatPllReg(pll_value_t *pPLL)
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{
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unsigned int ulPllReg = 0;
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@ -73,7 +73,6 @@ initchip_param_t;
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logical_chip_type_t getChipType(void);
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unsigned int calcPllValue(unsigned int request, pll_value_t *pll);
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unsigned int calcPllValue2(unsigned int, pll_value_t *);
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unsigned int formatPllReg(pll_value_t *pPLL);
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void ddk750_set_mmio(void __iomem *, unsigned short, char);
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unsigned int ddk750_getVMSize(void);
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