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clk: rockchip: mark noc and some special clk as critical on rk3288
The atclk/dbg/jtag/hsic-xin12m/pclk_core clks no driver to handle them. But this clks need enable,so make it as ignore_unused for now. The ddrupctl0/ddrupctl1/publ0/publ1 clks no driver to handle them, Chip design requirements for these clock to always on, The pmu_hclk_otg0 is Chip design defect, must be always on, Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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parent
f18c0994cd
commit
55bb6a633c
1 changed files with 10 additions and 4 deletions
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@ -292,13 +292,13 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
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RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
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RK3288_CLKGATE_CON(12), 6, GFLAGS),
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COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
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COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED,
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RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
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RK3288_CLKGATE_CON(12), 7, GFLAGS),
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COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
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RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
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RK3288_CLKGATE_CON(12), 8, GFLAGS),
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GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
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GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
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RK3288_CLKGATE_CON(12), 9, GFLAGS),
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GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
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RK3288_CLKGATE_CON(12), 10, GFLAGS),
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@ -626,7 +626,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
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RK3288_CLKSEL_CON(22), 7, IFLAGS),
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GATE(0, "jtag", "ext_jtag", 0,
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GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
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RK3288_CLKGATE_CON(4), 14, GFLAGS),
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COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
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@ -635,7 +635,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
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RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
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RK3288_CLKGATE_CON(3), 6, GFLAGS),
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GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
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GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED,
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RK3288_CLKGATE_CON(13), 9, GFLAGS),
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DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
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RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
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@ -816,6 +816,12 @@ static const char *const rk3288_critical_clocks[] __initconst = {
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"pclk_alive_niu",
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"pclk_pd_pmu",
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"pclk_pmu_niu",
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"pclk_core_niu",
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"pclk_ddrupctl0",
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"pclk_publ0",
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"pclk_ddrupctl1",
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"pclk_publ1",
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"pmu_hclk_otg0",
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};
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static void __iomem *rk3288_cru_base;
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