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platform: mellanox: Add field upgrade capability register
Add new register to indicate the method of FPGA/CPLD field upgrade supported on the specific system. Currently two masks are available: b00 - field upgrade through LPC gateway (new method introduced to accelerate field upgrade process). b11 - field upgrade through CPU GPIO pins (old method). Signed-off-by: Vadim Pasternak <vadimp@nvidia.com> Reviewed-by: Michael Shych <michaelsh@nvidia.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Link: https://lore.kernel.org/r/20230822113451.13785-3-vadimp@nvidia.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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1 changed files with 12 additions and 0 deletions
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@ -62,6 +62,7 @@
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#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37
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#define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a
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#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b
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#define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET 0x3c
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#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40
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#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41
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#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42
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@ -236,6 +237,7 @@
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#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4)
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#define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0)
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#define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0)
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#define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0)
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#define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0)
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#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6)
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#define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3)
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@ -3680,6 +3682,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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.mask = GENMASK(7, 0) & ~BIT(6),
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.mode = 0200,
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},
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{
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.label = "jtag_cap",
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.reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET,
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.mask = MLXPLAT_CPLD_FU_CAP_MASK,
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.bit = 1,
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.mode = 0444,
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},
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{
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.label = "jtag_enable",
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.reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET,
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@ -4935,6 +4944,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:
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case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
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@ -5046,6 +5056,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
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@ -5203,6 +5214,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:
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