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wil6210: new SW reset
New firmware allows for shorter SW reset procedure. After SW reset, FW raises "fw done" IRQ, at this moment mailbox control structures are initialized, driver caches it. New status bit wil_status_reset_done introduced to track completion of the reset. It is set by "fw ready" irq, and required for WMI rx flow to access control structures. WMI Tx flow protected by other status bit, wil_status_fwready. It can't be set before wil_status_reset_done is set by design. Signed-off-by: Vladimir Kondratiev <qca_vkondrat@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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parent
c7996ef852
commit
55f7acdd24
4 changed files with 17 additions and 23 deletions
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@ -240,6 +240,15 @@ static void wil_notify_fw_error(struct wil6210_priv *wil)
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kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
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}
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static void wil_cache_mbox_regs(struct wil6210_priv *wil)
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{
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/* make shadow copy of registers that should not change on run time */
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wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
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sizeof(struct wil6210_mbox_ctl));
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wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
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wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
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}
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static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
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{
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struct wil6210_priv *wil = cookie;
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@ -268,6 +277,8 @@ static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
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if (isr & ISR_MISC_FW_READY) {
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wil_dbg_irq(wil, "IRQ: FW ready\n");
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wil_cache_mbox_regs(wil);
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set_bit(wil_status_reset_done, &wil->status);
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/**
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* Actual FW ready indicated by the
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* WMI_FW_READY_EVENTID
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@ -103,15 +103,6 @@ static void wil_connect_timer_fn(ulong x)
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schedule_work(&wil->disconnect_worker);
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}
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static void wil_cache_mbox_regs(struct wil6210_priv *wil)
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{
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/* make shadow copy of registers that should not change on run time */
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wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
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sizeof(struct wil6210_mbox_ctl));
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wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
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wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
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}
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static void wil_connect_worker(struct work_struct *work)
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{
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int rc;
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@ -161,8 +152,6 @@ int wil_priv_init(struct wil6210_priv *wil)
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return -EAGAIN;
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}
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wil_cache_mbox_regs(wil);
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return 0;
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}
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@ -199,15 +188,11 @@ static void wil_target_reset(struct wil6210_priv *wil)
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W(RGF_USER_MAC_CPU_0, BIT(1)); /* mac_cpu_man_rst */
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W(RGF_USER_USER_CPU_0, BIT(1)); /* user_cpu_man_rst */
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msleep(100);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003F);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000170);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xFFE7FC00);
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msleep(100);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);
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@ -217,12 +202,6 @@ static void wil_target_reset(struct wil6210_priv *wil)
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00000080);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
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msleep(2000);
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W(RGF_USER_USER_CPU_0, BIT(0)); /* user_cpu_man_de_rst */
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msleep(2000);
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wil_dbg_misc(wil, "Reset completed\n");
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#undef W
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@ -279,8 +258,6 @@ int wil_reset(struct wil6210_priv *wil)
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wil->pending_connect_cid = -1;
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INIT_COMPLETION(wil->wmi_ready);
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wil_cache_mbox_regs(wil);
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/* TODO: release MAC reset */
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wil6210_enable_irq(wil);
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@ -186,6 +186,7 @@ enum { /* for wil6210_priv.status */
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wil_status_fwready = 0,
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wil_status_fwconnected,
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wil_status_dontscan,
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wil_status_reset_done,
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wil_status_irqen, /* FIXME: interrupts enabled - for debug */
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};
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@ -585,6 +585,11 @@ void wmi_recv_cmd(struct wil6210_priv *wil)
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void __iomem *src;
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ulong flags;
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if (!test_bit(wil_status_reset_done, &wil->status)) {
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wil_err(wil, "Reset not completed\n");
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return;
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}
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for (;;) {
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u16 len;
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