MIPS: Ingenic: Refresh device tree for Ingenic SoCs and boards.
1.Add SSI nodes for X1000 SoC and X1830 SoC from Ingenic. 2.Refresh SSI related nodes in CU1000-Neo and CU1830-Neo. 3.The X1830 SoC used by the CU1830-Neo and the X1000 SoC used by the CU1000-Neo are both single-core processors, therefore the "OST_CLK_PERCPU_TIMER" ABI should not be used in the OST nodes of the CU1830-Neo and CU1000-Neo, it is just a coincidence that there is no problem now. So replace the misused "OST_CLK_PERCPU_TIMER" ABI with the correct "OST_CLK_EVENT_TIMER" ABI. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
周琰杰 (Zhou Yanjie)
Thomas Bogendoerfer
parent
b2a5df7134
commit
562dc4c9c2
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@ -31,42 +31,6 @@
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};
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};
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ssi: spi-gpio {
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compatible = "spi-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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num-chipselects = <1>;
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mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
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miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
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sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
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cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
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status = "okay";
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spi-max-frequency = <50000000>;
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sc16is752: expander@0 {
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compatible = "nxp,sc16is752";
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reg = <0>; /* CE0 */
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spi-max-frequency = <4000000>;
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clocks = <&exclk_sc16is752>;
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interrupt-parent = <&gpc>;
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interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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exclk_sc16is752: sc16is752 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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};
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wlan_pwrseq: msc1-pwrseq {
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compatible = "mmc-pwrseq-simple";
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@ -90,7 +54,7 @@
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&ost {
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/* 1500 kHz for the system timer and clocksource */
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assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
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assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
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assigned-clock-rates = <1500000>, <1500000>;
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};
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@ -101,6 +65,39 @@
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pinctrl-0 = <&pins_uart2>;
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};
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&ssi {
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status = "okay";
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num-cs = <2>;
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cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pins_ssi>;
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sc16is752: expander@0 {
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compatible = "nxp,sc16is752";
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reg = <0>; /* CE0 */
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spi-rx-bus-width = <1>;
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spi-tx-bus-width = <1>;
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spi-max-frequency = <4000000>;
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clocks = <&exclk_sc16is752>;
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interrupt-parent = <&gpc>;
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interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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exclk_sc16is752: sc16is752 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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};
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&i2c0 {
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status = "okay";
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@ -192,6 +189,12 @@
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bias-pull-up;
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};
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pins_ssi: ssi {
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function = "ssi";
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groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d";
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bias-disable;
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};
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pins_i2c0: i2c0 {
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function = "i2c0";
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groups = "i2c0-data";
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@ -31,42 +31,6 @@
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};
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};
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ssi0: spi-gpio {
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compatible = "spi-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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num-chipselects = <1>;
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mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
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miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
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sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
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cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
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status = "okay";
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spi-max-frequency = <50000000>;
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sc16is752: expander@0 {
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compatible = "nxp,sc16is752";
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reg = <0>; /* CE0 */
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spi-max-frequency = <4000000>;
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clocks = <&exclk_sc16is752>;
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interrupt-parent = <&gpb>;
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interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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exclk_sc16is752: sc16is752 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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};
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wlan_pwrseq: msc1-pwrseq {
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compatible = "mmc-pwrseq-simple";
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@ -90,7 +54,7 @@
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&ost {
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/* 1500 kHz for the system timer and clocksource */
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assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
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assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
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assigned-clock-rates = <1500000>, <1500000>;
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};
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@ -101,6 +65,38 @@
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pinctrl-0 = <&pins_uart1>;
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};
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&ssi0 {
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status = "okay";
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num-cs = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pins_ssi0>;
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sc16is752: expander@0 {
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compatible = "nxp,sc16is752";
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reg = <0>; /* CE0 */
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spi-rx-bus-width = <1>;
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spi-tx-bus-width = <1>;
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spi-max-frequency = <4000000>;
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clocks = <&exclk_sc16is752>;
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interrupt-parent = <&gpb>;
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interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
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gpio-controller;
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#gpio-cells = <2>;
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exclk_sc16is752: sc16is752 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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};
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&i2c0 {
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status = "okay";
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@ -196,6 +192,12 @@
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bias-pull-up;
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};
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pins_ssi0: ssi0 {
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function = "ssi0";
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groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
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bias-disable;
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};
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pins_i2c0: i2c0 {
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function = "i2c0";
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groups = "i2c0-data";
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@ -258,6 +258,25 @@
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status = "disabled";
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};
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ssi: spi@10043000 {
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compatible = "ingenic,x1000-spi";
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reg = <0x10043000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <8>;
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clocks = <&cgu X1000_CLK_SSI>;
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clock-names = "spi";
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dmas = <&pdma X1000_DMA_SSI0_RX 0xffffffff>,
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<&pdma X1000_DMA_SSI0_TX 0xffffffff>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c0: i2c-controller@10050000 {
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compatible = "ingenic,x1000-i2c";
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reg = <0x10050000 0x1000>;
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@ -303,6 +322,7 @@
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pdma: dma-controller@13420000 {
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compatible = "ingenic,x1000-dma";
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reg = <0x13420000 0x400>, <0x13421000 0x40>;
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#dma-cells = <2>;
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interrupt-parent = <&intc>;
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@ -240,6 +240,44 @@
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status = "disabled";
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};
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ssi0: spi@10043000 {
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compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
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reg = <0x10043000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <9>;
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clocks = <&cgu X1830_CLK_SSI0>;
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clock-names = "spi";
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dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>,
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<&pdma X1830_DMA_SSI0_TX 0xffffffff>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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ssi1: spi@10044000 {
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compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
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reg = <0x10044000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&intc>;
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interrupts = <8>;
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clocks = <&cgu X1830_CLK_SSI1>;
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clock-names = "spi";
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dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>,
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<&pdma X1830_DMA_SSI1_TX 0xffffffff>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c0: i2c-controller@10050000 {
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compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
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reg = <0x10050000 0x1000>;
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@ -294,6 +332,7 @@
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pdma: dma-controller@13420000 {
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compatible = "ingenic,x1830-dma";
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reg = <0x13420000 0x400>, <0x13421000 0x40>;
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#dma-cells = <2>;
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interrupt-parent = <&intc>;
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