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drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)
Allows you to force multiple levels rather than just one via the new sysfs interrface. v2: squash in: drm/amd/powerplay: ensure clock level set by user is valid. From Rex. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
5122438954
commit
5632708f44
8 changed files with 81 additions and 34 deletions
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@ -362,16 +362,23 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
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struct amdgpu_device *adev = ddev->dev_private;
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int ret;
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long level;
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uint32_t i, mask = 0;
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char sub_str[2];
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ret = kstrtol(buf, 0, &level);
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for (i = 0; i < strlen(buf) - 1; i++) {
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sub_str[0] = *(buf + i);
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sub_str[1] = '\0';
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ret = kstrtol(sub_str, 0, &level);
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if (ret) {
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count = -EINVAL;
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goto fail;
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if (ret) {
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count = -EINVAL;
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goto fail;
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}
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mask |= 1 << level;
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}
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if (adev->pp_enabled)
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amdgpu_dpm_force_clock_level(adev, PP_SCLK, level);
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amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
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fail:
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return count;
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}
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@ -399,16 +406,23 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
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struct amdgpu_device *adev = ddev->dev_private;
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int ret;
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long level;
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uint32_t i, mask = 0;
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char sub_str[2];
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ret = kstrtol(buf, 0, &level);
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for (i = 0; i < strlen(buf) - 1; i++) {
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sub_str[0] = *(buf + i);
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sub_str[1] = '\0';
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ret = kstrtol(sub_str, 0, &level);
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if (ret) {
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count = -EINVAL;
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goto fail;
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if (ret) {
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count = -EINVAL;
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goto fail;
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}
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mask |= 1 << level;
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}
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if (adev->pp_enabled)
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amdgpu_dpm_force_clock_level(adev, PP_MCLK, level);
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amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
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fail:
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return count;
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}
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@ -436,16 +450,23 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
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struct amdgpu_device *adev = ddev->dev_private;
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int ret;
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long level;
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uint32_t i, mask = 0;
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char sub_str[2];
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ret = kstrtol(buf, 0, &level);
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for (i = 0; i < strlen(buf) - 1; i++) {
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sub_str[0] = *(buf + i);
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sub_str[1] = '\0';
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ret = kstrtol(sub_str, 0, &level);
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if (ret) {
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count = -EINVAL;
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goto fail;
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if (ret) {
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count = -EINVAL;
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goto fail;
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}
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mask |= 1 << level;
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}
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if (adev->pp_enabled)
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amdgpu_dpm_force_clock_level(adev, PP_PCIE, level);
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amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
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fail:
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return count;
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}
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@ -763,7 +763,7 @@ static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
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}
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static int pp_dpm_force_clock_level(void *handle,
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enum pp_clock_type type, int level)
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enum pp_clock_type type, uint32_t mask)
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{
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struct pp_hwmgr *hwmgr;
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@ -779,7 +779,7 @@ static int pp_dpm_force_clock_level(void *handle,
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return 0;
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}
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return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, level);
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return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
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}
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static int pp_dpm_print_clock_levels(void *handle,
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@ -1729,7 +1729,7 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
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}
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static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, int level)
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enum pp_clock_type type, uint32_t mask)
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{
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
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return -EINVAL;
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@ -1738,10 +1738,10 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
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case PP_SCLK:
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetSclkSoftMin,
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(1 << level));
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mask);
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SetSclkSoftMax,
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(1 << level));
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mask);
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break;
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default:
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break;
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@ -5113,7 +5113,7 @@ static int fiji_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t siz
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}
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static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, int level)
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enum pp_clock_type type, uint32_t mask)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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@ -5125,20 +5125,30 @@ static int fiji_force_clock_level(struct pp_hwmgr *hwmgr,
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if (!data->sclk_dpm_key_disabled)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SCLKDPM_SetEnabledMask,
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(1 << level));
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data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
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break;
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case PP_MCLK:
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if (!data->mclk_dpm_key_disabled)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_MCLKDPM_SetEnabledMask,
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(1 << level));
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data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
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break;
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case PP_PCIE:
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{
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uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
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uint32_t level = 0;
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while (tmp >>= 1)
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level++;
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if (!data->pcie_dpm_key_disabled)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_PCIeDPM_ForceLevel,
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(1 << level));
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level);
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break;
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}
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default:
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break;
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}
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@ -4767,7 +4767,7 @@ static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_
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}
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static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, int level)
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enum pp_clock_type type, uint32_t mask)
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{
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struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
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@ -4779,20 +4779,28 @@ static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr,
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if (!data->sclk_dpm_key_disabled)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SCLKDPM_SetEnabledMask,
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(1 << level));
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data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
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break;
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case PP_MCLK:
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if (!data->mclk_dpm_key_disabled)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_MCLKDPM_SetEnabledMask,
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(1 << level));
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data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
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break;
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case PP_PCIE:
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{
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uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
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uint32_t level = 0;
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while (tmp >>= 1)
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level++;
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if (!data->pcie_dpm_key_disabled)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_PCIeDPM_ForceLevel,
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(1 << level));
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level);
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break;
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}
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default:
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break;
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}
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@ -6075,7 +6075,7 @@ static int tonga_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t si
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}
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static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, int level)
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enum pp_clock_type type, uint32_t mask)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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@ -6087,20 +6087,28 @@ static int tonga_force_clock_level(struct pp_hwmgr *hwmgr,
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if (!data->sclk_dpm_key_disabled)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_SCLKDPM_SetEnabledMask,
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(1 << level));
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data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
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break;
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case PP_MCLK:
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if (!data->mclk_dpm_key_disabled)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_MCLKDPM_SetEnabledMask,
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(1 << level));
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data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);
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break;
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case PP_PCIE:
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{
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uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask;
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uint32_t level = 0;
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while (tmp >>= 1)
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level++;
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if (!data->pcie_dpm_key_disabled)
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smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_PCIeDPM_ForceLevel,
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(1 << level));
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level);
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break;
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}
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default:
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break;
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}
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@ -340,7 +340,7 @@ struct amd_powerplay_funcs {
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int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
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int (*get_pp_table)(void *handle, char **table);
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int (*set_pp_table)(void *handle, const char *buf, size_t size);
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int (*force_clock_level)(void *handle, enum pp_clock_type type, int level);
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int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
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int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
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};
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@ -335,7 +335,7 @@ struct pp_hwmgr_func {
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int (*power_off_asic)(struct pp_hwmgr *hwmgr);
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int (*get_pp_table)(struct pp_hwmgr *hwmgr, char **table);
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int (*set_pp_table)(struct pp_hwmgr *hwmgr, const char *buf, size_t size);
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int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, int level);
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int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
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int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
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int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);
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};
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