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drm/amdgpu: S3 resume fail on Polaris10
Sometimes, driver can not return from fence waiting when doing VCE ring ib test. The issue is a asic special and random issue. so adjust VCE suspend and resume sequence. Signed-off-by: JimQu <Jim.Qu@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
f476852a8c
commit
567e6e2984
1 changed files with 96 additions and 45 deletions
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@ -43,6 +43,7 @@
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x8616
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x8617
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#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x8618
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#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
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#define VCE_V3_0_FW_SIZE (384 * 1024)
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#define VCE_V3_0_STACK_SIZE (64 * 1024)
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@ -51,6 +52,7 @@
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static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
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static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
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static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
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static int vce_v3_0_wait_for_idle(void *handle);
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/**
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* vce_v3_0_ring_get_rptr - get read pointer
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@ -205,6 +207,32 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
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vce_v3_0_override_vce_clock_gating(adev, false);
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}
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static int vce_v3_0_firmware_loaded(struct amdgpu_device *adev)
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{
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int i, j;
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uint32_t status = 0;
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for (i = 0; i < 10; ++i) {
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for (j = 0; j < 100; ++j) {
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status = RREG32(mmVCE_STATUS);
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if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
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return 0;
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mdelay(10);
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}
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DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
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WREG32_P(mmVCE_SOFT_RESET,
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VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(10);
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WREG32_P(mmVCE_SOFT_RESET, 0,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(10);
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}
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return -ETIMEDOUT;
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}
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/**
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* vce_v3_0_start - start VCE block
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*
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@ -215,11 +243,24 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
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static int vce_v3_0_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring;
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int idx, i, j, r;
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int idx, r;
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ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, ring->wptr);
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WREG32(mmVCE_RB_WPTR, ring->wptr);
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WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
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ring = &adev->vce.ring[1];
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WREG32(mmVCE_RB_RPTR2, ring->wptr);
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WREG32(mmVCE_RB_WPTR2, ring->wptr);
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WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
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mutex_lock(&adev->grbm_idx_mutex);
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for (idx = 0; idx < 2; ++idx) {
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if (adev->vce.harvest_config & (1 << idx))
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continue;
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@ -233,48 +274,24 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
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vce_v3_0_mc_resume(adev, idx);
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/* set BUSY flag */
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WREG32_P(mmVCE_STATUS, 1, ~1);
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WREG32_P(mmVCE_STATUS, VCE_STATUS__JOB_BUSY_MASK,
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~VCE_STATUS__JOB_BUSY_MASK);
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if (adev->asic_type >= CHIP_STONEY)
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WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001);
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else
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WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK,
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~VCE_VCPU_CNTL__CLK_EN_MASK);
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WREG32_P(mmVCE_SOFT_RESET,
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VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
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WREG32_P(mmVCE_SOFT_RESET, 0,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(100);
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WREG32_P(mmVCE_SOFT_RESET, 0,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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for (i = 0; i < 10; ++i) {
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uint32_t status;
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for (j = 0; j < 100; ++j) {
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status = RREG32(mmVCE_STATUS);
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if (status & 2)
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break;
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mdelay(10);
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}
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r = 0;
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if (status & 2)
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break;
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DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
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WREG32_P(mmVCE_SOFT_RESET,
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VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(10);
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WREG32_P(mmVCE_SOFT_RESET, 0,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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mdelay(10);
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r = -1;
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}
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r = vce_v3_0_firmware_loaded(adev);
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/* clear BUSY flag */
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WREG32_P(mmVCE_STATUS, 0, ~1);
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WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
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/* Set Clock-Gating off */
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if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
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@ -290,19 +307,46 @@ static int vce_v3_0_start(struct amdgpu_device *adev)
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WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
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mutex_unlock(&adev->grbm_idx_mutex);
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ring = &adev->vce.ring[0];
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WREG32(mmVCE_RB_RPTR, ring->wptr);
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WREG32(mmVCE_RB_WPTR, ring->wptr);
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WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
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return 0;
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}
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ring = &adev->vce.ring[1];
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WREG32(mmVCE_RB_RPTR2, ring->wptr);
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WREG32(mmVCE_RB_WPTR2, ring->wptr);
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WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
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WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
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WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
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static int vce_v3_0_stop(struct amdgpu_device *adev)
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{
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int idx;
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mutex_lock(&adev->grbm_idx_mutex);
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for (idx = 0; idx < 2; ++idx) {
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if (adev->vce.harvest_config & (1 << idx))
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continue;
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if (idx == 0)
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WREG32_P(mmGRBM_GFX_INDEX, 0,
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~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
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else
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WREG32_P(mmGRBM_GFX_INDEX,
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GRBM_GFX_INDEX__VCE_INSTANCE_MASK,
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~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
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if (adev->asic_type >= CHIP_STONEY)
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WREG32_P(mmVCE_VCPU_CNTL, 0, ~0x200001);
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else
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WREG32_P(mmVCE_VCPU_CNTL, 0,
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~VCE_VCPU_CNTL__CLK_EN_MASK);
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/* hold on ECPU */
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WREG32_P(mmVCE_SOFT_RESET,
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VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
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~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
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/* clear BUSY flag */
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WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
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/* Set Clock-Gating off */
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if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
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vce_v3_0_set_vce_sw_clock_gating(adev, false);
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}
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WREG32_P(mmGRBM_GFX_INDEX, 0, ~GRBM_GFX_INDEX__VCE_INSTANCE_MASK);
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mutex_unlock(&adev->grbm_idx_mutex);
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return 0;
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}
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@ -441,7 +485,14 @@ static int vce_v3_0_hw_init(void *handle)
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static int vce_v3_0_hw_fini(void *handle)
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{
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return 0;
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = vce_v3_0_wait_for_idle(handle);
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if (r)
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return r;
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return vce_v3_0_stop(adev);
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}
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static int vce_v3_0_suspend(void *handle)
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