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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-06 02:50:43 +00:00
drm/i915: Use VMA for scratch page tracking
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1471254551-25805-19-git-send-email-chris@chris-wilson.co.uk
This commit is contained in:
parent
57e8853181
commit
56c0f1a7c1
6 changed files with 46 additions and 43 deletions
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@ -660,7 +660,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
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MI_STORE_REGISTER_MEM |
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MI_SRM_LRM_GLOBAL_GTT);
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intel_ring_emit_reg(ring, last_reg);
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intel_ring_emit(ring, engine->scratch.gtt_offset);
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intel_ring_emit(ring, engine->scratch->node.start);
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intel_ring_emit(ring, MI_NOOP);
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}
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intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
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@ -1101,7 +1101,7 @@ static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
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if (HAS_BROKEN_CS_TLB(dev_priv))
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ee->wa_batchbuffer =
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i915_error_ggtt_object_create(dev_priv,
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engine->scratch.obj);
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engine->scratch->obj);
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if (request->ctx->engine[i].state) {
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ee->ctx = i915_error_ggtt_object_create(dev_priv,
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@ -11795,7 +11795,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
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intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
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MI_SRM_LRM_GLOBAL_GTT);
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intel_ring_emit_reg(ring, DERRMR);
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intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256);
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intel_ring_emit(ring, req->engine->scratch->node.start + 256);
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if (IS_GEN8(dev)) {
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, MI_NOOP);
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@ -914,7 +914,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
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wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
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MI_SRM_LRM_GLOBAL_GTT));
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wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
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wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
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wa_ctx_emit(batch, index, engine->scratch->node.start + 256);
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wa_ctx_emit(batch, index, 0);
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wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
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@ -932,7 +932,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
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wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
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MI_SRM_LRM_GLOBAL_GTT));
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wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
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wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
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wa_ctx_emit(batch, index, engine->scratch->node.start + 256);
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wa_ctx_emit(batch, index, 0);
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return index;
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@ -993,7 +993,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
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/* WaClearSlmSpaceAtContextSwitch:bdw,chv */
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/* Actual scratch location is at 128 bytes offset */
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scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
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scratch_addr = engine->scratch->node.start + 2 * CACHELINE_BYTES;
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wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
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wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
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@ -1072,8 +1072,8 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
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/* WaClearSlmSpaceAtContextSwitch:kbl */
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/* Actual scratch location is at 128 bytes offset */
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if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
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uint32_t scratch_addr
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= engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
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u32 scratch_addr =
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engine->scratch->node.start + 2 * CACHELINE_BYTES;
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wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
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wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
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@ -1215,7 +1215,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
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}
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/* some WA perform writes to scratch page, ensure it is valid */
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if (engine->scratch.obj == NULL) {
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if (!engine->scratch) {
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DRM_ERROR("scratch page not allocated for %s\n", engine->name);
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return -EINVAL;
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}
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@ -1483,7 +1483,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
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{
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struct intel_ring *ring = request->ring;
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struct intel_engine_cs *engine = request->engine;
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u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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u32 scratch_addr = engine->scratch->node.start + 2 * CACHELINE_BYTES;
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bool vf_flush_wa = false, dc_flush_wa = false;
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u32 flags = 0;
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int ret;
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@ -1844,11 +1844,11 @@ int logical_render_ring_init(struct intel_engine_cs *engine)
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else
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engine->init_hw = gen8_init_render_ring;
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engine->init_context = gen8_init_rcs_context;
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engine->cleanup = intel_fini_pipe_control;
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engine->cleanup = intel_engine_cleanup_scratch;
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engine->emit_flush = gen8_emit_flush_render;
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engine->emit_request = gen8_emit_request_render;
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ret = intel_init_pipe_control(engine, 4096);
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ret = intel_engine_create_scratch(engine, 4096);
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if (ret)
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return ret;
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@ -176,7 +176,7 @@ intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
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{
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struct intel_ring *ring = req->ring;
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u32 scratch_addr =
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req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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req->engine->scratch->node.start + 2 * CACHELINE_BYTES;
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int ret;
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ret = intel_ring_begin(req, 6);
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@ -212,7 +212,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
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{
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struct intel_ring *ring = req->ring;
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u32 scratch_addr =
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req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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req->engine->scratch->node.start + 2 * CACHELINE_BYTES;
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u32 flags = 0;
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int ret;
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@ -286,7 +286,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
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{
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struct intel_ring *ring = req->ring;
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u32 scratch_addr =
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req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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req->engine->scratch->node.start + 2 * CACHELINE_BYTES;
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u32 flags = 0;
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int ret;
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@ -370,7 +370,8 @@ gen8_emit_pipe_control(struct drm_i915_gem_request *req,
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static int
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gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode)
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{
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u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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u32 scratch_addr =
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req->engine->scratch->node.start + 2 * CACHELINE_BYTES;
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u32 flags = 0;
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int ret;
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@ -612,45 +613,51 @@ static int init_ring_common(struct intel_engine_cs *engine)
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return ret;
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}
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void intel_fini_pipe_control(struct intel_engine_cs *engine)
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void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
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{
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if (engine->scratch.obj == NULL)
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struct i915_vma *vma;
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vma = fetch_and_zero(&engine->scratch);
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if (!vma)
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return;
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i915_gem_object_ggtt_unpin(engine->scratch.obj);
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i915_gem_object_put(engine->scratch.obj);
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engine->scratch.obj = NULL;
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i915_vma_unpin(vma);
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i915_vma_put(vma);
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}
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int intel_init_pipe_control(struct intel_engine_cs *engine, int size)
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int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int ret;
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WARN_ON(engine->scratch.obj);
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WARN_ON(engine->scratch);
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obj = i915_gem_object_create_stolen(&engine->i915->drm, size);
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if (!obj)
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obj = i915_gem_object_create(&engine->i915->drm, size);
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if (IS_ERR(obj)) {
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DRM_ERROR("Failed to allocate scratch page\n");
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ret = PTR_ERR(obj);
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goto err;
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return PTR_ERR(obj);
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}
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ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 4096, PIN_HIGH);
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vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err_unref;
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}
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ret = i915_vma_pin(vma, 0, 4096, PIN_GLOBAL | PIN_HIGH);
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if (ret)
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goto err_unref;
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engine->scratch.obj = obj;
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engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
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DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
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engine->name, engine->scratch.gtt_offset);
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engine->scratch = vma;
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DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08llx\n",
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engine->name, vma->node.start);
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return 0;
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err_unref:
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i915_gem_object_put(engine->scratch.obj);
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err:
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i915_gem_object_put(obj);
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return ret;
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}
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@ -1305,7 +1312,7 @@ static void render_ring_cleanup(struct intel_engine_cs *engine)
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dev_priv->semaphore_obj = NULL;
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}
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intel_fini_pipe_control(engine);
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intel_engine_cleanup_scratch(engine);
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}
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static int gen8_rcs_signal(struct drm_i915_gem_request *req)
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@ -1763,7 +1770,7 @@ i830_emit_bb_start(struct drm_i915_gem_request *req,
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unsigned int dispatch_flags)
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{
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struct intel_ring *ring = req->ring;
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u32 cs_offset = req->engine->scratch.gtt_offset;
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u32 cs_offset = req->engine->scratch->node.start;
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int ret;
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ret = intel_ring_begin(req, 6);
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@ -2793,11 +2800,11 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
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return ret;
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if (INTEL_GEN(dev_priv) >= 6) {
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ret = intel_init_pipe_control(engine, 4096);
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ret = intel_engine_create_scratch(engine, 4096);
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if (ret)
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return ret;
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} else if (HAS_BROKEN_CS_TLB(dev_priv)) {
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ret = intel_init_pipe_control(engine, I830_WA_SIZE);
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ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
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if (ret)
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return ret;
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}
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@ -198,6 +198,7 @@ struct intel_engine_cs {
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struct intel_hw_status_page status_page;
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struct i915_ctx_workarounds wa_ctx;
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struct i915_vma *scratch;
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u32 irq_keep_mask; /* always keep these interrupts */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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struct intel_engine_hangcheck hangcheck;
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struct {
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struct drm_i915_gem_object *obj;
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u32 gtt_offset;
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} scratch;
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bool needs_cmd_parser;
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/*
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@ -476,8 +472,8 @@ void intel_ring_update_space(struct intel_ring *ring);
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void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
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int intel_init_pipe_control(struct intel_engine_cs *engine, int size);
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void intel_fini_pipe_control(struct intel_engine_cs *engine);
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int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
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void intel_engine_cleanup_scratch(struct intel_engine_cs *engine);
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void intel_engine_setup_common(struct intel_engine_cs *engine);
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int intel_engine_init_common(struct intel_engine_cs *engine);
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