davinci: dm6467/T EVM: fix setting up of reference clock rate

The DM6467 and DM6467T EVMs use different reference clock
frequencies. This difference is currently supported by having
the SoC code call a public board routine which sets up the reference
clock frequency. This does not scale as more boards are added.

Instead, use the clk_set_rate() API to setup the reference clock
frequency to a different value from the board file.

Suggested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Kevin Hilman <khilman@ti.com>
This commit is contained in:
Sekhar Nori 2011-06-14 15:33:20 +00:00
parent 0c6fce5eb6
commit 56e580d778
5 changed files with 49 additions and 14 deletions

View file

@ -719,9 +719,15 @@ static void __init cdce_clk_init(void)
} }
} }
#define DM6467T_EVM_REF_FREQ 33000000
static void __init davinci_map_io(void) static void __init davinci_map_io(void)
{ {
dm646x_init(); dm646x_init();
if (machine_is_davinci_dm6467tevm())
davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
cdce_clk_init(); cdce_clk_init();
} }
@ -785,17 +791,6 @@ static __init void evm_init(void)
soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID; soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
} }
#define DM646X_EVM_REF_FREQ 27000000
#define DM6467T_EVM_REF_FREQ 33000000
void __init dm646x_board_setup_refclk(struct clk *clk)
{
if (machine_is_davinci_dm6467tevm())
clk->rate = DM6467T_EVM_REF_FREQ;
else
clk->rate = DM646X_EVM_REF_FREQ;
}
MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.boot_params = (0x80000100), .boot_params = (0x80000100),
.map_io = davinci_map_io, .map_io = davinci_map_io,

View file

@ -368,6 +368,12 @@ static unsigned long clk_leafclk_recalc(struct clk *clk)
return clk->parent->rate; return clk->parent->rate;
} }
int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
{
clk->rate = rate;
return 0;
}
static unsigned long clk_pllclk_recalc(struct clk *clk) static unsigned long clk_pllclk_recalc(struct clk *clk)
{ {
u32 ctrl, mult = 1, prediv = 1, postdiv = 1; u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
@ -506,6 +512,38 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
} }
EXPORT_SYMBOL(davinci_set_pllrate); EXPORT_SYMBOL(davinci_set_pllrate);
/**
* davinci_set_refclk_rate() - Set the reference clock rate
* @rate: The new rate.
*
* Sets the reference clock rate to a given value. This will most likely
* result in the entire clock tree getting updated.
*
* This is used to support boards which use a reference clock different
* than that used by default in <soc>.c file. The reference clock rate
* should be updated early in the boot process; ideally soon after the
* clock tree has been initialized once with the default reference clock
* rate (davinci_common_init()).
*
* Returns 0 on success, error otherwise.
*/
int davinci_set_refclk_rate(unsigned long rate)
{
struct clk *refclk;
refclk = clk_get(NULL, "ref");
if (IS_ERR(refclk)) {
pr_err("%s: failed to get reference clock.\n", __func__);
return PTR_ERR(refclk);
}
clk_set_rate(refclk, rate);
clk_put(refclk);
return 0;
}
int __init davinci_clk_init(struct clk_lookup *clocks) int __init davinci_clk_init(struct clk_lookup *clocks)
{ {
struct clk_lookup *c; struct clk_lookup *c;

View file

@ -123,6 +123,8 @@ int davinci_clk_init(struct clk_lookup *clocks);
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
unsigned int mult, unsigned int postdiv); unsigned int mult, unsigned int postdiv);
int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate); int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
int davinci_set_refclk_rate(unsigned long rate);
int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
extern struct platform_device davinci_wdt_device; extern struct platform_device davinci_wdt_device;
extern void davinci_watchdog_reset(struct platform_device *); extern void davinci_watchdog_reset(struct platform_device *);

View file

@ -42,6 +42,7 @@
/* /*
* Device specific clocks * Device specific clocks
*/ */
#define DM646X_REF_FREQ 27000000
#define DM646X_AUX_FREQ 24000000 #define DM646X_AUX_FREQ 24000000
static struct pll_data pll1_data = { static struct pll_data pll1_data = {
@ -56,6 +57,8 @@ static struct pll_data pll2_data = {
static struct clk ref_clk = { static struct clk ref_clk = {
.name = "ref_clk", .name = "ref_clk",
.rate = DM646X_REF_FREQ,
.set_rate = davinci_simple_set_rate,
}; };
static struct clk aux_clkin = { static struct clk aux_clkin = {
@ -901,7 +904,6 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv)
void __init dm646x_init(void) void __init dm646x_init(void)
{ {
dm646x_board_setup_refclk(&ref_clk);
davinci_common_init(&davinci_soc_info_dm646x); davinci_common_init(&davinci_soc_info_dm646x);
} }

View file

@ -15,7 +15,6 @@
#include <mach/asp.h> #include <mach/asp.h>
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/videodev2.h> #include <linux/videodev2.h>
#include <linux/clk.h>
#include <linux/davinci_emac.h> #include <linux/davinci_emac.h>
#define DM646X_EMAC_BASE (0x01C80000) #define DM646X_EMAC_BASE (0x01C80000)
@ -31,7 +30,6 @@
void __init dm646x_init(void); void __init dm646x_init(void);
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
void __init dm646x_board_setup_refclk(struct clk *clk);
int __init dm646x_init_edma(struct edma_rsv_info *rsv); int __init dm646x_init_edma(struct edma_rsv_info *rsv);
void dm646x_video_init(void); void dm646x_video_init(void);