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USB: dbgp: EHCI debug controller initialization delays
When using the EHCI host controller as a polled device, a bit more tolerance is required in terms of delays. On some 3+ghz systems the cpu loops were faster than the EHCI device mmio and resulted in the controller failing to initialize. On at least one first generation EHCI controller when it was not operating in interrupt mode, it would fail to report a port change status, but executing the port reset allowed the debug controller to work correctly anyway. This errata causes a one time 300ms delay in the boot time, where as the typical delay is 1-5ms for an EHCI controller that does not have this errata. The debug printk's were fixed to have the correct state messages, and there was a conversion from using early_printk to printk to avoid calling the dbgp driver while debugging the initialization. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
parent
093344e136
commit
56faf0f98f
1 changed files with 26 additions and 19 deletions
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@ -9,6 +9,12 @@
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#include <asm/pci-direct.h>
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#include <asm/fixmap.h>
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#ifdef DBGP_DEBUG
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# define dbgp_printk printk
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#else
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static inline void dbgp_printk(const char *fmt, ...) { }
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#endif
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static struct ehci_caps __iomem *ehci_caps;
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static struct ehci_regs __iomem *ehci_regs;
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static struct ehci_dbg_port __iomem *ehci_debug;
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@ -342,6 +348,7 @@ static int __init ehci_reset_port(int port)
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u32 delay_time, delay;
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int loop;
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dbgp_printk("ehci_reset_port %i\n", port);
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/* Reset the usb debug port */
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portsc = readl(&ehci_regs->port_status[port - 1]);
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portsc &= ~PORT_PE;
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@ -352,14 +359,17 @@ static int __init ehci_reset_port(int port)
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for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT;
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delay_time += delay) {
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dbgp_mdelay(delay);
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portsc = readl(&ehci_regs->port_status[port - 1]);
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if (!(portsc & PORT_RESET))
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break;
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}
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if (portsc & PORT_RESET) {
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/* force reset to complete */
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loop = 2;
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loop = 100 * 1000;
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writel(portsc & ~(PORT_RWC_BITS | PORT_RESET),
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&ehci_regs->port_status[port - 1]);
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do {
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udelay(1);
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portsc = readl(&ehci_regs->port_status[port-1]);
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} while ((portsc & PORT_RESET) && (--loop > 0));
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}
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@ -375,7 +385,6 @@ static int __init ehci_reset_port(int port)
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/* If we've finished resetting, then break out of the loop */
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if (!(portsc & PORT_RESET) && (portsc & PORT_PE))
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return 0;
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}
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return -EBUSY;
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}
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@ -384,24 +393,18 @@ static int __init ehci_wait_for_port(int port)
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u32 status;
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int ret, reps;
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for (reps = 0; reps < 3; reps++) {
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dbgp_mdelay(100);
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for (reps = 0; reps < 300; reps++) {
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status = readl(&ehci_regs->status);
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if (status & STS_PCD) {
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ret = ehci_reset_port(port);
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if (ret == 0)
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return 0;
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}
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if (status & STS_PCD)
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break;
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dbgp_mdelay(1);
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}
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ret = ehci_reset_port(port);
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if (ret == 0)
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return 0;
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return -ENOTCONN;
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}
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#ifdef DBGP_DEBUG
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# define dbgp_printk early_printk
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#else
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static inline void dbgp_printk(const char *fmt, ...) { }
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#endif
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typedef void (*set_debug_port_t)(int port);
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static void __init default_set_debug_port(int port)
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@ -520,7 +523,7 @@ static int __init ehci_setup(void)
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return -1;
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}
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loop = 100000;
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loop = 250 * 1000;
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/* Reset the EHCI controller */
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cmd = readl(&ehci_regs->command);
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cmd |= CMD_RESET;
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@ -540,6 +543,7 @@ static int __init ehci_setup(void)
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ctrl |= DBGP_OWNER;
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ctrl &= ~(DBGP_ENABLED | DBGP_INUSE);
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writel(ctrl, &ehci_debug->control);
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udelay(1);
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/* Start the ehci running */
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cmd = readl(&ehci_regs->command);
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@ -554,10 +558,13 @@ static int __init ehci_setup(void)
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loop = 10;
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do {
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status = readl(&ehci_regs->status);
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} while ((status & STS_HALT) && (--loop > 0));
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if (!(status & STS_HALT))
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break;
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udelay(1);
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} while (--loop > 0);
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if (!loop) {
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dbgp_printk("ehci can be started\n");
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dbgp_printk("ehci can not be started\n");
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return -1;
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}
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dbgp_printk("ehci started\n");
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