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drm/amdgpu: extend profiling mode.
in profiling mode, powerplay will fix power state as stable as possible.and disable gfx cg and LBPW feature. profile_standard: as a prerequisite, ensure power and thermal sustainable, set clocks ratio as close to the highest clock ratio as possible. profile_min_sclk: fix mclk as profile_normal, set lowest sclk profile_min_mclk: fix sclk as profile_normal, set lowest mclk profile_peak: set highest sclk and mclk, power and thermal not sustainable profile_exit: exit profile mode. enable gfx cg/lbpw feature. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
7f61bed0c4
commit
570272d229
6 changed files with 155 additions and 27 deletions
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@ -142,12 +142,15 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
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level = amdgpu_dpm_get_performance_level(adev);
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return snprintf(buf, PAGE_SIZE, "%s\n",
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(level & (AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
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(level & AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
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(level & AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
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(level & AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
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(level & AMD_DPM_FORCED_LEVEL_PROFILING) ? "profiling" :
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"unknown"));
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(level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
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(level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
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(level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
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(level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
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(level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
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(level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
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(level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
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(level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
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"unknown");
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}
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static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
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@ -176,9 +179,17 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
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level = AMD_DPM_FORCED_LEVEL_AUTO;
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} else if (strncmp("manual", buf, strlen("manual")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_MANUAL;
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} else if (strncmp("profile", buf, strlen("profile")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_PROFILING;
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} else {
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} else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
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} else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
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} else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
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} else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
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} else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
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level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
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} else {
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count = -EINVAL;
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goto fail;
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}
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@ -186,14 +197,6 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
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if (current_level == level)
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return count;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILING)
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amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_UNGATE);
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else if (level != AMD_DPM_FORCED_LEVEL_PROFILING &&
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current_level == AMD_DPM_FORCED_LEVEL_PROFILING)
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amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_GATE);
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if (adev->pp_enabled)
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amdgpu_dpm_force_performance_level(adev, level);
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else {
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@ -210,6 +213,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
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adev->pm.dpm.forced_level = level;
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mutex_unlock(&adev->pm.mutex);
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}
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fail:
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return count;
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}
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@ -6571,8 +6571,9 @@ static int ci_dpm_force_clock_level(struct amdgpu_device *adev,
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{
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struct ci_power_info *pi = ci_get_pi(adev);
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if (!(adev->pm.dpm.forced_level &
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(AMD_DPM_FORCED_LEVEL_MANUAL | AMD_DPM_FORCED_LEVEL_PROFILING)))
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if (adev->pm.dpm.forced_level & (AMD_DPM_FORCED_LEVEL_AUTO |
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AMD_DPM_FORCED_LEVEL_LOW |
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AMD_DPM_FORCED_LEVEL_HIGH))
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return -EINVAL;
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switch (type) {
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@ -85,7 +85,11 @@ enum amd_dpm_forced_level {
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AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
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AMD_DPM_FORCED_LEVEL_LOW = 0x4,
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AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
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AMD_DPM_FORCED_LEVEL_PROFILING = 0x10,
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AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
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AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
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};
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enum amd_powergating_state {
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@ -1650,8 +1650,7 @@ static int cz_get_dal_power_level(struct pp_hwmgr *hwmgr,
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static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, uint32_t mask)
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{
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if (!(hwmgr->dpm_level &
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(AMD_DPM_FORCED_LEVEL_MANUAL | AMD_DPM_FORCED_LEVEL_PROFILING)))
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
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return -EINVAL;
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switch (type) {
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@ -90,6 +90,8 @@ enum DPM_EVENT_SRC {
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};
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static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
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static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, uint32_t mask);
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static struct smu7_power_state *cast_phw_smu7_power_state(
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struct pp_hw_power_state *hw_ps)
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@ -2488,36 +2490,152 @@ static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
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}
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return 0;
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}
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static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
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uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
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{
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uint32_t percentage;
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
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int32_t tmp_mclk;
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int32_t tmp_sclk;
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int32_t count;
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if (golden_dpm_table->mclk_table.count < 1)
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return -EINVAL;
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percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value /
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golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
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if (golden_dpm_table->mclk_table.count == 1) {
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percentage = 70;
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tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value;
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*mclk_mask = golden_dpm_table->mclk_table.count - 1;
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} else {
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tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value;
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*mclk_mask = golden_dpm_table->mclk_table.count - 2;
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}
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tmp_sclk = tmp_mclk * percentage / 100;
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if (hwmgr->pp_table_version == PP_TABLE_V0) {
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for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
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count >= 0; count--) {
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if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
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tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
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*sclk_mask = count;
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break;
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}
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}
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if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
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*sclk_mask = 0;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
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*sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
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} else if (hwmgr->pp_table_version == PP_TABLE_V1) {
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) {
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if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) {
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tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk;
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*sclk_mask = count;
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break;
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}
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}
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if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
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*sclk_mask = 0;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
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*sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
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}
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
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*mclk_mask = 0;
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else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
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*mclk_mask = golden_dpm_table->mclk_table.count - 1;
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*pcie_mask = data->dpm_table.pcie_speed_table.count - 1;
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return 0;
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}
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static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
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enum amd_dpm_forced_level level)
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{
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int ret = 0;
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uint32_t sclk_mask = 0;
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uint32_t mclk_mask = 0;
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uint32_t pcie_mask = 0;
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uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
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if (level == hwmgr->dpm_level)
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return ret;
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if (!(hwmgr->dpm_level & profile_mode_mask)) {
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/* enter profile mode, save current level, disable gfx cg*/
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if (level & profile_mode_mask) {
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hwmgr->saved_dpm_level = hwmgr->dpm_level;
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_UNGATE);
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}
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} else {
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/* exit profile mode, restore level, enable gfx cg*/
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if (!(level & profile_mode_mask)) {
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
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level = hwmgr->saved_dpm_level;
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_GFX,
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AMD_CG_STATE_GATE);
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}
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}
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switch (level) {
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case AMD_DPM_FORCED_LEVEL_HIGH:
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ret = smu7_force_dpm_highest(hwmgr);
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if (ret)
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return ret;
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hwmgr->dpm_level = level;
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break;
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case AMD_DPM_FORCED_LEVEL_LOW:
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ret = smu7_force_dpm_lowest(hwmgr);
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if (ret)
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return ret;
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hwmgr->dpm_level = level;
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break;
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case AMD_DPM_FORCED_LEVEL_AUTO:
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ret = smu7_unforce_dpm_levels(hwmgr);
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if (ret)
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return ret;
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hwmgr->dpm_level = level;
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
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case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
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case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
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ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
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if (ret)
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return ret;
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hwmgr->dpm_level = level;
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smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
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smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
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smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
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break;
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case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
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default:
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break;
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}
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hwmgr->dpm_level = level;
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if (level & (AMD_DPM_FORCED_LEVEL_PROFILE_PEAK | AMD_DPM_FORCED_LEVEL_HIGH))
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smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
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else
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smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
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return ret;
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return 0;
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}
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static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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if (!(hwmgr->dpm_level &
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(AMD_DPM_FORCED_LEVEL_MANUAL | AMD_DPM_FORCED_LEVEL_PROFILING)))
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if (hwmgr->dpm_level & (AMD_DPM_FORCED_LEVEL_AUTO |
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AMD_DPM_FORCED_LEVEL_LOW |
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AMD_DPM_FORCED_LEVEL_HIGH))
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return -EINVAL;
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switch (type) {
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@ -612,6 +612,7 @@ struct pp_hwmgr {
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uint32_t num_vce_state_tables;
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enum amd_dpm_forced_level dpm_level;
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enum amd_dpm_forced_level saved_dpm_level;
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bool block_hw_access;
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struct phm_gfx_arbiter gfx_arbiter;
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struct phm_acp_arbiter acp_arbiter;
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