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ARM: gemini: Add missing register definitions for gemini timer
Add missing register defintions for the gemini clocksource Also do some #define' cleanup to make the code more readable. Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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2 changed files with 54 additions and 32 deletions
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@ -57,9 +57,6 @@
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#define GEMINI_USB1_BASE 0x69000000
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#define GEMINI_BIG_ENDIAN_BASE 0x80000000
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#define GEMINI_TIMER1_BASE GEMINI_TIMER_BASE
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#define GEMINI_TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
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#define GEMINI_TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)
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/*
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* UART Clock when System clk is 150MHz
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@ -19,21 +19,46 @@
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/*
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* Register definitions for the timers
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*/
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#define TIMER_COUNT(BASE_ADDR) (BASE_ADDR + 0x00)
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#define TIMER_LOAD(BASE_ADDR) (BASE_ADDR + 0x04)
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#define TIMER_MATCH1(BASE_ADDR) (BASE_ADDR + 0x08)
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#define TIMER_MATCH2(BASE_ADDR) (BASE_ADDR + 0x0C)
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#define TIMER_CR(BASE_ADDR) (BASE_ADDR + 0x30)
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#define TIMER_1_CR_ENABLE (1 << 0)
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#define TIMER_1_CR_CLOCK (1 << 1)
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#define TIMER_1_CR_INT (1 << 2)
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#define TIMER_2_CR_ENABLE (1 << 3)
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#define TIMER_2_CR_CLOCK (1 << 4)
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#define TIMER_2_CR_INT (1 << 5)
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#define TIMER_3_CR_ENABLE (1 << 6)
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#define TIMER_3_CR_CLOCK (1 << 7)
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#define TIMER_3_CR_INT (1 << 8)
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#define TIMER1_BASE GEMINI_TIMER_BASE
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#define TIMER2_BASE (GEMINI_TIMER_BASE + 0x10)
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#define TIMER3_BASE (GEMINI_TIMER_BASE + 0x20)
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#define TIMER_COUNT(BASE) (IO_ADDRESS(BASE) + 0x00)
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#define TIMER_LOAD(BASE) (IO_ADDRESS(BASE) + 0x04)
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#define TIMER_MATCH1(BASE) (IO_ADDRESS(BASE) + 0x08)
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#define TIMER_MATCH2(BASE) (IO_ADDRESS(BASE) + 0x0C)
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#define TIMER_CR (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x30)
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#define TIMER_INTR_STATE (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x34)
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#define TIMER_INTR_MASK (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x38)
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#define TIMER_1_CR_ENABLE (1 << 0)
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#define TIMER_1_CR_CLOCK (1 << 1)
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#define TIMER_1_CR_INT (1 << 2)
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#define TIMER_2_CR_ENABLE (1 << 3)
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#define TIMER_2_CR_CLOCK (1 << 4)
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#define TIMER_2_CR_INT (1 << 5)
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#define TIMER_3_CR_ENABLE (1 << 6)
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#define TIMER_3_CR_CLOCK (1 << 7)
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#define TIMER_3_CR_INT (1 << 8)
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#define TIMER_1_CR_UPDOWN (1 << 9)
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#define TIMER_2_CR_UPDOWN (1 << 10)
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#define TIMER_3_CR_UPDOWN (1 << 11)
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#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \
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TIMER_3_CR_ENABLE | \
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TIMER_3_CR_UPDOWN)
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#define TIMER_1_INT_MATCH1 (1 << 0)
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#define TIMER_1_INT_MATCH2 (1 << 1)
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#define TIMER_1_INT_OVERFLOW (1 << 2)
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#define TIMER_2_INT_MATCH1 (1 << 3)
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#define TIMER_2_INT_MATCH2 (1 << 4)
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#define TIMER_2_INT_OVERFLOW (1 << 5)
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#define TIMER_3_INT_MATCH1 (1 << 6)
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#define TIMER_3_INT_MATCH2 (1 << 7)
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#define TIMER_3_INT_OVERFLOW (1 << 8)
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#define TIMER_INT_ALL_MASK 0x1ff
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static unsigned int tick_rate;
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@ -42,19 +67,19 @@ static int gemini_timer_set_next_event(unsigned long cycles,
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{
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u32 cr;
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cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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cr = readl(TIMER_CR);
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/* This may be overdoing it, feel free to test without this */
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cr &= ~TIMER_2_CR_ENABLE;
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cr &= ~TIMER_2_CR_INT;
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writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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writel(cr, TIMER_CR);
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/* Set next event */
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writel(cycles, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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writel(cycles, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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writel(cycles, TIMER_COUNT(TIMER2_BASE));
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writel(cycles, TIMER_LOAD(TIMER2_BASE));
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cr |= TIMER_2_CR_ENABLE;
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cr |= TIMER_2_CR_INT;
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writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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writel(cr, TIMER_CR);
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return 0;
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}
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@ -67,10 +92,10 @@ static int gemini_timer_shutdown(struct clock_event_device *evt)
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* Disable also for oneshot: the set_next() call will arm the timer
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* instead.
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*/
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cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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cr = readl(TIMER_CR);
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cr &= ~TIMER_2_CR_ENABLE;
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cr &= ~TIMER_2_CR_INT;
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writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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writel(cr, TIMER_CR);
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return 0;
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}
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@ -80,12 +105,12 @@ static int gemini_timer_set_periodic(struct clock_event_device *evt)
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u32 cr;
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/* Start the timer */
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writel(period, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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writel(period, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER2_BASE)));
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cr = readl(TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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writel(period, TIMER_COUNT(TIMER2_BASE));
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writel(period, TIMER_LOAD(TIMER2_BASE));
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cr = readl(TIMER_CR);
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cr |= TIMER_2_CR_ENABLE;
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cr |= TIMER_2_CR_INT;
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writel(cr, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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writel(cr, TIMER_CR);
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return 0;
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}
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@ -155,10 +180,10 @@ void __init gemini_timer_init(void)
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setup_irq(IRQ_TIMER2, &gemini_timer_irq);
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/* Enable and use TIMER1 as clock source */
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writel(0xffffffff, TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)));
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writel(0xffffffff, TIMER_LOAD(IO_ADDRESS(GEMINI_TIMER1_BASE)));
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writel(TIMER_1_CR_ENABLE, TIMER_CR(IO_ADDRESS(GEMINI_TIMER_BASE)));
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if (clocksource_mmio_init(TIMER_COUNT(IO_ADDRESS(GEMINI_TIMER1_BASE)),
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writel(0xffffffff, TIMER_COUNT(TIMER1_BASE));
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writel(0xffffffff, TIMER_LOAD(TIMER1_BASE));
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writel(TIMER_1_CR_ENABLE, TIMER_CR);
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if (clocksource_mmio_init(TIMER_COUNT(TIMER1_BASE),
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"TIMER1", tick_rate, 300, 32,
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clocksource_mmio_readl_up))
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pr_err("timer: failed to initialize gemini clock source\n");
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