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sh: disable aliased page logic on NOMMU models
SH3/4 (with MMU) have a virtually indexed cache, requiring explicit work to avoid consistency problems arising from having the same physical address range cached in multiple cache lines. This is unneeded for the NOMMU case, and some of the resulting code paths (kmap_coherent) don't work. SH2 only avoided this problem by having a 4-way associative cache with way size equal to the page size (4k), yielding no cache index bits outside of the page offset and thus no aliases. Signed-off-by: Rich Felker <dalias@libc.org>
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2 changed files with 8 additions and 0 deletions
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@ -323,9 +323,13 @@ asmlinkage void cpu_init(void)
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cache_init();
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cache_init();
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if (raw_smp_processor_id() == 0) {
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if (raw_smp_processor_id() == 0) {
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#ifdef CONFIG_MMU
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shm_align_mask = max_t(unsigned long,
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shm_align_mask = max_t(unsigned long,
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current_cpu_data.dcache.way_size - 1,
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current_cpu_data.dcache.way_size - 1,
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PAGE_SIZE - 1);
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PAGE_SIZE - 1);
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#else
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shm_align_mask = PAGE_SIZE - 1;
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#endif
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/* Boot CPU sets the cache shape */
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/* Boot CPU sets the cache shape */
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detect_cache_shape();
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detect_cache_shape();
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@ -244,7 +244,11 @@ void flush_cache_sigtramp(unsigned long address)
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static void compute_alias(struct cache_info *c)
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static void compute_alias(struct cache_info *c)
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{
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{
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#ifdef CONFIG_MMU
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c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
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c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
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#else
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c->alias_mask = 0;
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#endif
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c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
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c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
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}
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}
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