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crypto: caam - set RDB bit in security configuration register
This change is required for post SEC-5.0 devices which have RNG4. Setting RDB in security configuration register allows CAAM to use the "Random Data Buffer" to be filled by a single request. The Random Data Buffer is large enough for ten packets to get their IVs from a single request. If the Random Data Buffer is not enabled, then each IV causes a separate request, and RNG4 hardware cannot keep up resulting in lower IPSEC throughput if random IVs are used. Signed-off-by: Vakul Garg <vakul@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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a80c5422b1
commit
575c1bd549
2 changed files with 6 additions and 1 deletions
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@ -304,6 +304,9 @@ static int caam_probe(struct platform_device *pdev)
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caam_remove(pdev);
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return ret;
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}
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/* Enable RDB bit so that RNG works faster */
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setbits32(&topregs->ctrl.scfgr, SCFGR_RDBENABLE);
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}
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/* NOTE: RTIC detection ought to go here, around Si time */
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@ -252,7 +252,8 @@ struct caam_ctrl {
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/* Read/Writable */
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u32 rsvd1;
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u32 mcr; /* MCFG Master Config Register */
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u32 rsvd2[2];
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u32 rsvd2;
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u32 scfgr; /* SCFGR, Security Config Register */
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/* Bus Access Configuration Section 010-11f */
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/* Read/Writable */
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@ -299,6 +300,7 @@ struct caam_ctrl {
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#define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
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#define MCFGR_DMA_RESET 0x10000000
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#define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
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#define SCFGR_RDBENABLE 0x00000400
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/* AXI read cache control */
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#define MCFGR_ARCACHE_SHIFT 12
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