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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Non-critical fix for the pclk_edp divider on rk3399, one new clock-id
and making niu (interconnect) clocks critical on rk3288, as CLK_IGNORE_UNUSED is not enough to keep them running all the time when more users access particular clock subtrees. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAliRFEMQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgWHMB/0ZQ1p88CmxkN8kiaJBkO8UpmLuRrPivXoH HiZBN9fvxdR7DcrhQvH8kSt2Ir9h3Rc22TzPWChcwq1io66Bd8BuXkPP/vP9am8J It0VeERQzyHTLY++DYTsBmQmuaxPRm9cFsxLY5i4vowipjinFj/gDDX6DIg97j2p r0ytQQhOM47sRhfJSrGFsfXZIa5z5Ty0Qg04ESGmvIllrMUlm9N7+U667qknkYLW j2T7jWAK2l3RVe9AC7Bf10l7sldzHPHY5MuQ5WiFUWW3OgJyIUKJbD8jythg9i8V +54LsmX3HkIjS1OiIwECtU1Nv2t8w9RqDRCubzp/Yf+ff+oDL0h3 =VeAF -----END PGP SIGNATURE----- Merge tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk updates from Heiko Stuebner: "Non-critical fix for the pclk_edp divider on rk3399, one new clock-id and making niu (interconnect) clocks critical on rk3288, as CLK_IGNORE_UNUSED is not enough to keep them running all the time when more users access particular clock subtrees." * tag 'v4.11-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3288: make all niu clocks critical clk: rockchip: use rk3288 vip_out clock ids clk: rockchip: add rk3288 vip_out clock id clk: rockchip: fix the incorrect pclk_edp div width for RK3399
This commit is contained in:
commit
5775a4c76f
3 changed files with 17 additions and 9 deletions
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@ -468,7 +468,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
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RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
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RK3288_CLKGATE_CON(3), 7, GFLAGS),
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COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
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COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
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RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
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DIV(0, "pclk_pd_alive", "gpll", 0,
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@ -689,7 +689,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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/* aclk_peri gates */
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GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
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GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
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GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS),
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GATE(0, "aclk_peri_niu", "aclk_peri", 0, RK3288_CLKGATE_CON(7), 11, GFLAGS),
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GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
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GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
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GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
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@ -752,12 +752,12 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
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GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
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GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
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GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS),
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GATE(0, "pclk_alive_niu", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 12, GFLAGS),
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/* pclk_pd_pmu gates */
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GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
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GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
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GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS),
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GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 2, GFLAGS),
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GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
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GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
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@ -766,7 +766,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
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GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
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GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
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GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS),
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GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 10, GFLAGS),
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GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
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GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
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GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
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@ -782,17 +782,17 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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/* aclk_vio0 gates */
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GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
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GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
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GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS),
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GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 11, GFLAGS),
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GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
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/* aclk_vio1 gates */
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GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
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GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
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GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS),
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GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 12, GFLAGS),
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/* aclk_rga_pre gates */
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GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
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GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS),
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GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 13, GFLAGS),
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/*
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* Other ungrouped clocks.
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@ -807,8 +807,15 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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static const char *const rk3288_critical_clocks[] __initconst = {
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"aclk_cpu",
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"aclk_peri",
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"aclk_peri_niu",
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"aclk_vio0_niu",
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"aclk_vio1_niu",
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"aclk_rga_niu",
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"hclk_peri",
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"hclk_vio_niu",
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"pclk_alive_niu",
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"pclk_pd_pmu",
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"pclk_pmu_niu",
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};
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static void __iomem *rk3288_cru_base;
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@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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RK3399_CLKGATE_CON(11), 8, GFLAGS),
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COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
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RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
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RK3399_CLKGATE_CON(11), 11, GFLAGS),
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GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
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RK3399_CLKGATE_CON(32), 12, GFLAGS),
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@ -88,6 +88,7 @@
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#define SCLK_PVTM_GPU 124
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#define SCLK_CRYPTO 125
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#define SCLK_MIPIDSI_24M 126
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#define SCLK_VIP_OUT 127
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#define SCLK_MAC 151
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#define SCLK_MACREF_OUT 152
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