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drm/amd/powerplay: Setup sw CTF to allow graceful exit when temperature exceeds maximum.
cherry-pick from amd windows driver. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
652bd0c344
commit
5784d5cca6
1 changed files with 45 additions and 28 deletions
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@ -381,14 +381,10 @@ int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
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temp = cgs_read_register(hwmgr->device, reg);
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temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
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CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
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temp = (temp & CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK) >>
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CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT;
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/* Bit 9 means the reading is lower than the lowest usable value. */
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if (temp & 0x200)
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temp = VEGA10_THERMAL_MAXIMUM_TEMP_READING;
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else
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temp = temp & 0x1ff;
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temp = temp & 0x1ff;
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temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
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@ -424,23 +420,28 @@ static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
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mmTHM_THERMAL_INT_CTRL_BASE_IDX, mmTHM_THERMAL_INT_CTRL);
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val = cgs_read_register(hwmgr->device, reg);
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val &= ~(THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK);
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val |= (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) <<
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THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT;
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val &= ~(THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
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val |= (low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) <<
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THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT;
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val &= (~THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK);
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val |= (5 << THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT);
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val &= (~THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK);
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val |= (1 << THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT);
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val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK);
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val |= ((high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
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<< THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT);
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val &= (~THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK);
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val |= ((low / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
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<< THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT);
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val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
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cgs_write_register(hwmgr->device, reg, val);
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reg = soc15_get_register_offset(THM_HWID, 0,
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mmTHM_TCON_HTC_BASE_IDX, mmTHM_TCON_HTC);
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val = cgs_read_register(hwmgr->device, reg);
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val &= ~(THM_TCON_HTC__HTC_TMP_LMT_MASK);
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val |= (high / PP_TEMPERATURE_UNITS_PER_CENTIGRADES) <<
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THM_TCON_HTC__HTC_TMP_LMT__SHIFT;
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cgs_write_register(hwmgr->device, reg, val);
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return 0;
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}
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@ -482,18 +483,28 @@ static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
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static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
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{
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struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
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uint32_t val = 0;
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uint32_t reg;
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if (data->smu_features[GNLD_FW_CTF].supported) {
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if (data->smu_features[GNLD_FW_CTF].enabled)
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printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
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PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
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true,
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data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
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"Attempt to Enable FW CTF feature Failed!",
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return -1);
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data->smu_features[GNLD_FW_CTF].enabled = true;
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}
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PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
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true,
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data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
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"Attempt to Enable FW CTF feature Failed!",
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return -1);
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data->smu_features[GNLD_FW_CTF].enabled = true;
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val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
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val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
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val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
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reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
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cgs_write_register(hwmgr->device, reg, val);
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return 0;
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}
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@ -504,18 +515,24 @@ static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
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int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
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{
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struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
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uint32_t reg;
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if (data->smu_features[GNLD_FW_CTF].supported) {
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if (!data->smu_features[GNLD_FW_CTF].enabled)
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printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
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}
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PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
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PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr,
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false,
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data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
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"Attempt to disable FW CTF feature Failed!",
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return -1);
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data->smu_features[GNLD_FW_CTF].enabled = false;
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data->smu_features[GNLD_FW_CTF].enabled = false;
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}
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reg = soc15_get_register_offset(THM_HWID, 0, mmTHM_THERMAL_INT_ENA_BASE_IDX, mmTHM_THERMAL_INT_ENA);
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cgs_write_register(hwmgr->device, reg, 0);
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return 0;
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}
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