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KVM: arm64: Delay the polling of the GICR_VPENDBASER.Dirty bit
In order to reduce the impact of the VPT parsing happening on the GIC, we can split the vcpu reseidency in two phases: - programming GICR_VPENDBASER: this still happens in vcpu_load() - checking for the VPT parsing to be complete: this can happen on vcpu entry (in kvm_vgic_flush_hwstate()) This allows the GIC and the CPU to work in parallel, rewmoving some of the entry overhead. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Shenming Lu <lushenming@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20201128141857.983-3-lushenming@huawei.com
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parent
bf118a5cb7
commit
57e3cebd02
6 changed files with 47 additions and 4 deletions
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@ -353,6 +353,18 @@ int vgic_v4_load(struct kvm_vcpu *vcpu)
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return err;
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}
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void vgic_v4_commit(struct kvm_vcpu *vcpu)
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{
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struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe;
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/*
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* No need to wait for the vPE to be ready across a shallow guest
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* exit, as only a vcpu_put will invalidate it.
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*/
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if (!vpe->ready)
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its_commit_vpe(vpe);
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}
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static struct vgic_its *vgic_get_its(struct kvm *kvm,
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struct kvm_kernel_irq_routing_entry *irq_entry)
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{
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@ -915,6 +915,9 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
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if (can_access_vgic_from_kernel())
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vgic_restore_state(vcpu);
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if (vgic_supports_direct_msis(vcpu->kvm))
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vgic_v4_commit(vcpu);
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}
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void kvm_vgic_load(struct kvm_vcpu *vcpu)
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@ -3842,8 +3842,6 @@ static void its_vpe_schedule(struct its_vpe *vpe)
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val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
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val |= GICR_VPENDBASER_Valid;
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gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
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its_wait_vpt_parse_complete();
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}
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static void its_vpe_deschedule(struct its_vpe *vpe)
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@ -3891,6 +3889,10 @@ static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
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its_vpe_deschedule(vpe);
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return 0;
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case COMMIT_VPE:
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its_wait_vpt_parse_complete();
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return 0;
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case INVALL_VPE:
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its_vpe_invall(vpe);
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return 0;
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@ -4052,8 +4054,6 @@ static void its_vpe_4_1_schedule(struct its_vpe *vpe,
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val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id);
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gicr_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
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its_wait_vpt_parse_complete();
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}
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static void its_vpe_4_1_deschedule(struct its_vpe *vpe,
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@ -4128,6 +4128,10 @@ static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
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its_vpe_4_1_deschedule(vpe, info);
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return 0;
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case COMMIT_VPE:
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its_wait_vpt_parse_complete();
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return 0;
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case INVALL_VPE:
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its_vpe_4_1_invall(vpe);
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return 0;
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@ -232,6 +232,8 @@ int its_make_vpe_non_resident(struct its_vpe *vpe, bool db)
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if (!ret)
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vpe->resident = false;
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vpe->ready = false;
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return ret;
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}
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@ -258,6 +260,23 @@ int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en)
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return ret;
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}
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int its_commit_vpe(struct its_vpe *vpe)
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{
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struct its_cmd_info info = {
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.cmd_type = COMMIT_VPE,
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};
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int ret;
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WARN_ON(preemptible());
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ret = its_send_vpe_cmd(vpe, &info);
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if (!ret)
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vpe->ready = true;
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return ret;
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}
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int its_invall_vpe(struct its_vpe *vpe)
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{
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struct its_cmd_info info = {
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@ -402,6 +402,7 @@ int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int irq,
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struct kvm_kernel_irq_routing_entry *irq_entry);
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int vgic_v4_load(struct kvm_vcpu *vcpu);
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void vgic_v4_commit(struct kvm_vcpu *vcpu);
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int vgic_v4_put(struct kvm_vcpu *vcpu, bool need_db);
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#endif /* __KVM_ARM_VGIC_H */
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@ -39,6 +39,8 @@ struct its_vpe {
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irq_hw_number_t vpe_db_lpi;
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/* VPE resident */
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bool resident;
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/* VPT parse complete */
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bool ready;
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union {
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/* GICv4.0 implementations */
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struct {
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@ -104,6 +106,7 @@ enum its_vcpu_info_cmd_type {
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PROP_UPDATE_AND_INV_VLPI,
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SCHEDULE_VPE,
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DESCHEDULE_VPE,
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COMMIT_VPE,
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INVALL_VPE,
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PROP_UPDATE_VSGI,
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};
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@ -129,6 +132,7 @@ int its_alloc_vcpu_irqs(struct its_vm *vm);
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void its_free_vcpu_irqs(struct its_vm *vm);
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int its_make_vpe_resident(struct its_vpe *vpe, bool g0en, bool g1en);
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int its_make_vpe_non_resident(struct its_vpe *vpe, bool db);
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int its_commit_vpe(struct its_vpe *vpe);
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int its_invall_vpe(struct its_vpe *vpe);
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int its_map_vlpi(int irq, struct its_vlpi_map *map);
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int its_get_vlpi(int irq, struct its_vlpi_map *map);
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