mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 03:10:12 +00:00
clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks
Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks, so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX also update. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20201118135822.9582-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
parent
7f5b57a095
commit
5868491e12
1 changed files with 14 additions and 14 deletions
|
@ -255,19 +255,19 @@ static struct rockchip_clk_branch common_spdif_fracmux __initdata =
|
|||
RK2928_CLKSEL_CON(5), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch common_uart0_fracmux __initdata =
|
||||
MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0,
|
||||
MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch common_uart1_fracmux __initdata =
|
||||
MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0,
|
||||
MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch common_uart2_fracmux __initdata =
|
||||
MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0,
|
||||
MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch common_uart3_fracmux __initdata =
|
||||
MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0,
|
||||
MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch common_clk_branches[] __initdata = {
|
||||
|
@ -408,28 +408,28 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
|
|||
COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0,
|
||||
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 8, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
|
||||
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(17), 0,
|
||||
RK2928_CLKGATE_CON(1), 9, GFLAGS,
|
||||
&common_uart0_fracmux),
|
||||
COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
|
||||
RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 10, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
|
||||
COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(18), 0,
|
||||
RK2928_CLKGATE_CON(1), 11, GFLAGS,
|
||||
&common_uart1_fracmux),
|
||||
COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
|
||||
RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 12, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
|
||||
COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(19), 0,
|
||||
RK2928_CLKGATE_CON(1), 13, GFLAGS,
|
||||
&common_uart2_fracmux),
|
||||
COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
|
||||
RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(1), 14, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
|
||||
COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(20), 0,
|
||||
RK2928_CLKGATE_CON(1), 15, GFLAGS,
|
||||
&common_uart3_fracmux),
|
||||
|
@ -543,15 +543,15 @@ static struct clk_div_table div_aclk_cpu_t[] = {
|
|||
};
|
||||
|
||||
static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata =
|
||||
MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0,
|
||||
MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(2), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata =
|
||||
MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0,
|
||||
MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata =
|
||||
MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0,
|
||||
MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(4), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
|
||||
|
@ -615,21 +615,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
|
|||
COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0,
|
||||
RK2928_CLKSEL_CON(2), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 7, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
|
||||
COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(6), 0,
|
||||
RK2928_CLKGATE_CON(0), 8, GFLAGS,
|
||||
&rk3066a_i2s0_fracmux),
|
||||
COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
|
||||
RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 9, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0,
|
||||
COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(7), 0,
|
||||
RK2928_CLKGATE_CON(0), 10, GFLAGS,
|
||||
&rk3066a_i2s1_fracmux),
|
||||
COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
|
||||
RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
|
||||
RK2928_CLKGATE_CON(0), 11, GFLAGS),
|
||||
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0,
|
||||
COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", CLK_SET_RATE_PARENT,
|
||||
RK2928_CLKSEL_CON(8), 0,
|
||||
RK2928_CLKGATE_CON(0), 12, GFLAGS,
|
||||
&rk3066a_i2s2_fracmux),
|
||||
|
|
Loading…
Reference in a new issue