mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-30 08:02:30 +00:00
MIPS: Netlogic: Use PRID_IMP_MASK macro
Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor type. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6868/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
0d57eba02d
commit
5874743ea8
6 changed files with 10 additions and 9 deletions
|
@ -146,9 +146,9 @@ static inline int hard_smp_processor_id(void)
|
|||
|
||||
static inline int nlm_nodeid(void)
|
||||
{
|
||||
uint32_t prid = read_c0_prid();
|
||||
uint32_t prid = read_c0_prid() & PRID_IMP_MASK;
|
||||
|
||||
if ((prid & 0xff00) == PRID_IMP_NETLOGIC_XLP9XX)
|
||||
if (prid == PRID_IMP_NETLOGIC_XLP9XX)
|
||||
return (__read_32bit_c0_register($15, 1) >> 7) & 0x7;
|
||||
else
|
||||
return (__read_32bit_c0_register($15, 1) >> 5) & 0x3;
|
||||
|
|
|
@ -99,7 +99,7 @@ void *xlp_dt_init(void *fdtp);
|
|||
|
||||
static inline int cpu_is_xlpii(void)
|
||||
{
|
||||
int chip = read_c0_prid() & 0xff00;
|
||||
int chip = read_c0_prid() & PRID_IMP_MASK;
|
||||
|
||||
return chip == PRID_IMP_NETLOGIC_XLP2XX ||
|
||||
chip == PRID_IMP_NETLOGIC_XLP9XX;
|
||||
|
@ -107,7 +107,7 @@ static inline int cpu_is_xlpii(void)
|
|||
|
||||
static inline int cpu_is_xlp9xx(void)
|
||||
{
|
||||
int chip = read_c0_prid() & 0xff00;
|
||||
int chip = read_c0_prid() & PRID_IMP_MASK;
|
||||
|
||||
return chip == PRID_IMP_NETLOGIC_XLP9XX;
|
||||
}
|
||||
|
|
|
@ -35,6 +35,7 @@
|
|||
|
||||
#include <asm/asm.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/cacheops.h>
|
||||
#include <asm/regdef.h>
|
||||
#include <asm/mipsregs.h>
|
||||
|
@ -92,7 +93,7 @@
|
|||
*/
|
||||
.macro xlp_flush_l1_dcache
|
||||
mfc0 t0, CP0_EBASE, 0
|
||||
andi t0, t0, 0xff00
|
||||
andi t0, t0, PRID_IMP_MASK
|
||||
slt t1, t0, 0x1200
|
||||
beqz t1, 15f
|
||||
nop
|
||||
|
@ -171,7 +172,7 @@ FEXPORT(nlm_reset_entry)
|
|||
|
||||
1: /* Entry point on core wakeup */
|
||||
mfc0 t0, CP0_EBASE, 0 /* processor ID */
|
||||
andi t0, 0xff00
|
||||
andi t0, PRID_IMP_MASK
|
||||
li t1, 0x1500 /* XLP 9xx */
|
||||
beq t0, t1, 2f /* does not need to set coherent */
|
||||
nop
|
||||
|
|
|
@ -48,7 +48,7 @@ static void *xlp_fdt_blob;
|
|||
void __init *xlp_dt_init(void *fdtp)
|
||||
{
|
||||
if (!fdtp) {
|
||||
switch (current_cpu_data.processor_id & 0xff00) {
|
||||
switch (current_cpu_data.processor_id & PRID_IMP_MASK) {
|
||||
#ifdef CONFIG_DT_XLP_GVP
|
||||
case PRID_IMP_NETLOGIC_XLP9XX:
|
||||
fdtp = __dtb_xlp_gvp_begin;
|
||||
|
|
|
@ -121,7 +121,7 @@ void __init plat_mem_setup(void)
|
|||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
switch (read_c0_prid() & 0xff00) {
|
||||
switch (read_c0_prid() & PRID_IMP_MASK) {
|
||||
case PRID_IMP_NETLOGIC_XLP9XX:
|
||||
case PRID_IMP_NETLOGIC_XLP2XX:
|
||||
return "Broadcom XLPII Series";
|
||||
|
|
|
@ -139,7 +139,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
|
|||
} else {
|
||||
fusemask = nlm_read_sys_reg(nodep->sysbase,
|
||||
SYS_EFUSE_DEVICE_CFG_STATUS0);
|
||||
switch (read_c0_prid() & 0xff00) {
|
||||
switch (read_c0_prid() & PRID_IMP_MASK) {
|
||||
case PRID_IMP_NETLOGIC_XLP3XX:
|
||||
mask = 0xf;
|
||||
break;
|
||||
|
|
Loading…
Reference in a new issue