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clk: qcom: clk-rcg2: Update logic to calculate D value for RCG
The display pixel clock has a requirement on certain newer platforms to
support M/N as (2/3) and the final D value calculated results in
underflow errors.
As the current implementation does not check for D value is within
the accepted range for a given M & N value. Update the logic to
calculate the final D value based on the range.
Fixes: 99cbd064b0
("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@codeaurora.org
This commit is contained in:
parent
89f0f1a460
commit
58922910ad
1 changed files with 11 additions and 2 deletions
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@ -264,7 +264,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
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static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
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{
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u32 cfg, mask;
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u32 cfg, mask, d_val, not2d_val, n_minus_m;
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struct clk_hw *hw = &rcg->clkr.hw;
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int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
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@ -283,8 +283,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
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if (ret)
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return ret;
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/* Calculate 2d value */
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d_val = f->n;
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n_minus_m = f->n - f->m;
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n_minus_m *= 2;
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d_val = clamp_t(u32, d_val, f->m, n_minus_m);
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not2d_val = ~d_val & mask;
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ret = regmap_update_bits(rcg->clkr.regmap,
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RCG_D_OFFSET(rcg), mask, ~f->n);
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RCG_D_OFFSET(rcg), mask, not2d_val);
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if (ret)
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return ret;
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}
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