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arm64: dts: apq8096-db820c: enable bluetooth node
Add a new serial node for the Qualcomm BT controller QCA6174. This allows automatic probing and hci registration through the serdev framework instead of relying on the userspace helpers. Signed-off-by: Thierry Escande <thierry.escande@linaro.org> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
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4 changed files with 76 additions and 0 deletions
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@ -36,4 +36,30 @@ config {
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drive-strength = <2>; /* 2 MA */
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};
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};
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blsp1_uart1_default: blsp1_uart1_default {
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mux {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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function = "blsp_uart2";
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};
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config {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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drive-strength = <16>;
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bias-disable;
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};
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};
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blsp1_uart1_sleep: blsp1_uart1_sleep {
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mux {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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function = "gpio";
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};
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config {
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pins = "gpio41", "gpio42", "gpio43", "gpio44";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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@ -48,6 +48,16 @@ pinconf {
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};
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};
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divclk4_pin_a: divclk4 {
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pinconf {
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pins = "gpio18";
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function = PMIC_GPIO_FUNC_FUNC2;
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bias-disable;
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power-source = <PM8994_GPIO_S4>;
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};
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};
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usb3_vbus_det_gpio: pm8996_gpio22 {
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pinconf {
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pins = "gpio22";
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@ -23,6 +23,7 @@ / {
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aliases {
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serial0 = &blsp2_uart1;
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serial1 = &blsp2_uart2;
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serial2 = &blsp1_uart1;
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i2c0 = &blsp1_i2c2;
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i2c1 = &blsp2_i2c1;
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i2c2 = &blsp2_i2c0;
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@ -34,7 +35,36 @@ chosen {
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stdout-path = "serial0:115200n8";
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};
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clocks {
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divclk4: divclk4 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "divclk4";
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pinctrl-names = "default";
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pinctrl-0 = <&divclk4_pin_a>;
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};
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};
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soc {
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serial@7570000 {
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label = "BT-UART";
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_uart1_default>;
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pinctrl-1 = <&blsp1_uart1_sleep>;
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bluetooth {
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compatible = "qcom,qca6174-bt";
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/* bt_disable_n gpio */
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enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
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clocks = <&divclk4>;
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};
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};
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serial@75b0000 {
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label = "LS-UART1";
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status = "okay";
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@ -419,6 +419,16 @@ kryocc: clock-controller@6400000 {
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#clock-cells = <1>;
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};
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blsp1_uart1: serial@7570000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x07570000 0x1000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_spi0: spi@7575000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x07575000 0x600>;
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