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drm/amd/display: Program dpp dto based on actual dpp clk

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[Why]
dpp dto phase and modulo are programmed with actual dpp global clk
and pipe clk. Need to use actual dpp clk to prgoram dpp dto modulo
to get more accuracy ratio.

[How]
assign actual dpp clk to dccg for dpp modulo programming.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yongqiang Sun 2020-11-02 14:22:57 -05:00 committed by Alex Deucher
parent acf2740f12
commit 58cae8ac6b
1 changed files with 26 additions and 3 deletions
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29
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
View file

@ -103,6 +103,30 @@ void rn_set_low_power_state(struct clk_mgr *clk_mgr_base)
clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
} }
static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
struct dc_state *context, bool safe_to_lower)
{
int i;
clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.actual_dppclk_khz;
for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
int dpp_inst, dppclk_khz, prev_dppclk_khz;
/* Loop index will match dpp->inst if resource exists,
* and we want to avoid dependency on dpp object
*/
dpp_inst = i;
dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
clk_mgr->dccg->funcs->update_dpp_dto(
clk_mgr->dccg, dpp_inst, dppclk_khz);
}
}
void rn_update_clocks(struct clk_mgr *clk_mgr_base, void rn_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context, struct dc_state *context,
bool safe_to_lower) bool safe_to_lower)
@ -177,7 +201,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
if (dpp_clock_lowered) { if (dpp_clock_lowered) {
// increase per DPP DTO before lowering global dppclk // increase per DPP DTO before lowering global dppclk
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); rn_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
clk_mgr_base->clks.actual_dppclk_khz = clk_mgr_base->clks.actual_dppclk_khz =
rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
@ -188,7 +212,7 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); rn_vbios_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
// always update dtos unless clock is lowered and not safe to lower // always update dtos unless clock is lowered and not safe to lower
if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); rn_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
} }
if (update_dispclk && if (update_dispclk &&
@ -199,7 +223,6 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
} }
} }
static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr) static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
{ {
/* get FbMult value */ /* get FbMult value */