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clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment
PLL0 runs at 4.8 GHz, i.e. EXTAL x 100. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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1 changed files with 2 additions and 2 deletions
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@ -250,8 +250,8 @@ static const unsigned int r8a77990_crit_mod_clks[] __initconst = {
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/*
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* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
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*--------------------------------------------------------------------
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* 0 48 x 1 x100/4 x100/3 x100/3
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* 1 48 x 1 x100/4 x100/3 x58/3
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* 0 48 x 1 x100/1 x100/3 x100/3
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* 1 48 x 1 x100/1 x100/3 x58/3
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*/
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#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
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