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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-03 07:38:10 +00:00
clocking-wizard: Support higher frequency accuracy
Change the multipliers and divisors to support a higher frequency accuracy if there is only one output. Currently only O is changed now we are changing M, D and O. For multiple output case the earlier behavior is retained. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Link: https://lore.kernel.org/r/20230327062637.22237-1-shubhrajyoti.datta@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
parent
57e3bbd2cb
commit
595c88cda6
1 changed files with 204 additions and 24 deletions
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@ -8,12 +8,14 @@
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/iopoll.h>
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@ -37,6 +39,7 @@
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#define WZRD_CLKOUT_DIVIDE_MASK (0xff << WZRD_DIVCLK_DIVIDE_SHIFT)
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#define WZRD_CLKOUT_FRAC_SHIFT 8
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#define WZRD_CLKOUT_FRAC_MASK 0x3ff
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#define WZRD_CLKOUT0_FRAC_MASK GENMASK(17, 8)
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#define WZRD_DR_MAX_INT_DIV_VALUE 255
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#define WZRD_DR_STATUS_REG_OFFSET 0x04
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@ -49,6 +52,22 @@
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#define WZRD_USEC_POLL 10
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#define WZRD_TIMEOUT_POLL 1000
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/* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
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#define DIV_O 0x01
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#define DIV_ALL 0x03
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#define WZRD_M_MIN 2
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#define WZRD_M_MAX 128
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#define WZRD_D_MIN 1
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#define WZRD_D_MAX 106
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#define WZRD_VCO_MIN 800000000
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#define WZRD_VCO_MAX 1600000000
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#define WZRD_O_MIN 1
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#define WZRD_O_MAX 128
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#define WZRD_MIN_ERR 20000
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#define WZRD_FRAC_POINTS 1000
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/* Get the mask from width */
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#define div_mask(width) ((1 << (width)) - 1)
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@ -97,6 +116,9 @@ struct clk_wzrd {
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* @width: width of the divider bit field
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* @flags: clk_wzrd divider flags
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* @table: array of value/divider pairs, last entry should have div = 0
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* @m: value of the multiplier
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* @d: value of the common divider
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* @o: value of the leaf divider
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* @lock: register lock
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*/
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struct clk_wzrd_divider {
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@ -107,6 +129,9 @@ struct clk_wzrd_divider {
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u8 width;
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u8 flags;
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const struct clk_div_table *table;
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u32 m;
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u32 d;
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u32 o;
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spinlock_t *lock; /* divider lock */
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};
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@ -198,12 +223,155 @@ static long clk_wzrd_round_rate(struct clk_hw *hw, unsigned long rate,
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return *prate / div;
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}
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static int clk_wzrd_get_divisors(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
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unsigned long vco_freq, freq, diff;
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u32 m, d, o;
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for (m = WZRD_M_MIN; m <= WZRD_M_MAX; m++) {
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for (d = WZRD_D_MIN; d <= WZRD_D_MAX; d++) {
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vco_freq = DIV_ROUND_CLOSEST((parent_rate * m), d);
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if (vco_freq >= WZRD_VCO_MIN && vco_freq <= WZRD_VCO_MAX) {
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for (o = WZRD_O_MIN; o <= WZRD_O_MAX; o++) {
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freq = DIV_ROUND_CLOSEST_ULL(vco_freq, o);
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diff = abs(freq - rate);
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if (diff < WZRD_MIN_ERR) {
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divider->m = m;
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divider->d = d;
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divider->o = o;
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return 0;
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}
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}
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}
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}
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}
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return -EBUSY;
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}
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static int clk_wzrd_dynamic_all_nolock(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
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unsigned long vco_freq, rate_div, clockout0_div;
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u32 reg, pre, value, f;
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int err;
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err = clk_wzrd_get_divisors(hw, rate, parent_rate);
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if (err)
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return err;
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vco_freq = DIV_ROUND_CLOSEST(parent_rate * divider->m, divider->d);
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rate_div = DIV_ROUND_CLOSEST_ULL((vco_freq * WZRD_FRAC_POINTS), rate);
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clockout0_div = div_u64(rate_div, WZRD_FRAC_POINTS);
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pre = DIV_ROUND_CLOSEST_ULL(vco_freq * WZRD_FRAC_POINTS, rate);
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f = (pre - (clockout0_div * WZRD_FRAC_POINTS));
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f &= WZRD_CLKOUT_FRAC_MASK;
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reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, clockout0_div) |
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FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, f);
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writel(reg, divider->base + WZRD_CLK_CFG_REG(2));
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/* Set divisor and clear phase offset */
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reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |
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FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);
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writel(reg, divider->base + WZRD_CLK_CFG_REG(0));
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writel(divider->o, divider->base + WZRD_CLK_CFG_REG(2));
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writel(0, divider->base + WZRD_CLK_CFG_REG(3));
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/* Check status register */
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err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
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value & WZRD_DR_LOCK_BIT_MASK,
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WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
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if (err)
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return -ETIMEDOUT;
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/* Initiate reconfiguration */
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writel(WZRD_DR_BEGIN_DYNA_RECONF,
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divider->base + WZRD_DR_INIT_REG_OFFSET);
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/* Check status register */
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return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
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value & WZRD_DR_LOCK_BIT_MASK,
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WZRD_USEC_POLL, WZRD_TIMEOUT_POLL);
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}
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static int clk_wzrd_dynamic_all(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
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unsigned long flags = 0;
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int ret;
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spin_lock_irqsave(divider->lock, flags);
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ret = clk_wzrd_dynamic_all_nolock(hw, rate, parent_rate);
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spin_unlock_irqrestore(divider->lock, flags);
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return ret;
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}
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static unsigned long clk_wzrd_recalc_rate_all(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
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u32 m, d, o, div, reg, f;
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reg = readl(divider->base + WZRD_CLK_CFG_REG(0));
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d = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
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m = FIELD_GET(WZRD_CLKFBOUT_MULT_MASK, reg);
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reg = readl(divider->base + WZRD_CLK_CFG_REG(2));
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o = FIELD_GET(WZRD_DIVCLK_DIVIDE_MASK, reg);
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f = FIELD_GET(WZRD_CLKOUT0_FRAC_MASK, reg);
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div = DIV_ROUND_CLOSEST(d * (WZRD_FRAC_POINTS * o + f), WZRD_FRAC_POINTS);
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return divider_recalc_rate(hw, parent_rate * m, div, divider->table,
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divider->flags, divider->width);
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}
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static long clk_wzrd_round_rate_all(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
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unsigned long int_freq;
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u32 m, d, o, div, f;
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int err;
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err = clk_wzrd_get_divisors(hw, rate, *prate);
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if (err)
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return err;
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m = divider->m;
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d = divider->d;
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o = divider->o;
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div = d * o;
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int_freq = divider_recalc_rate(hw, *prate * m, div, divider->table,
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divider->flags, divider->width);
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if (rate > int_freq) {
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f = DIV_ROUND_CLOSEST_ULL(rate * WZRD_FRAC_POINTS, int_freq);
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rate = DIV_ROUND_CLOSEST(int_freq * f, WZRD_FRAC_POINTS);
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}
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return rate;
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}
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static const struct clk_ops clk_wzrd_clk_divider_ops = {
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.round_rate = clk_wzrd_round_rate,
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.set_rate = clk_wzrd_dynamic_reconfig,
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.recalc_rate = clk_wzrd_recalc_rate,
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};
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static const struct clk_ops clk_wzrd_clk_div_all_ops = {
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.round_rate = clk_wzrd_round_rate_all,
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.set_rate = clk_wzrd_dynamic_all,
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.recalc_rate = clk_wzrd_recalc_rate_all,
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};
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static unsigned long clk_wzrd_recalc_ratef(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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void __iomem *base, u16 offset,
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u8 shift, u8 width,
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u8 clk_divider_flags,
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const struct clk_div_table *table,
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u32 div_type,
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spinlock_t *lock)
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{
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struct clk_wzrd_divider *div;
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div->flags = clk_divider_flags;
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div->lock = lock;
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div->hw.init = &init;
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div->table = table;
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hw = &div->hw;
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ret = devm_clk_hw_register(dev, hw);
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void __iomem *base, u16 offset,
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u8 shift, u8 width,
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u8 clk_divider_flags,
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const struct clk_div_table *table,
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u32 div_type,
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spinlock_t *lock)
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{
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struct clk_wzrd_divider *div;
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@ -337,7 +504,12 @@ static struct clk *clk_wzrd_register_divider(struct device *dev,
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_wzrd_clk_divider_ops;
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if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
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init.ops = &clk_divider_ro_ops;
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else if (div_type == DIV_O)
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init.ops = &clk_wzrd_clk_divider_ops;
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else
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init.ops = &clk_wzrd_clk_div_all_ops;
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init.flags = flags;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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div->flags = clk_divider_flags;
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div->lock = lock;
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div->hw.init = &init;
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div->table = table;
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hw = &div->hw;
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ret = devm_clk_hw_register(dev, hw);
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@ -425,6 +596,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
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const char *clk_name;
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void __iomem *ctrl_reg;
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struct clk_wzrd *clk_wzrd;
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const char *clkout_name;
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struct device_node *np = pdev->dev.of_node;
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int nr_outputs;
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unsigned long flags = 0;
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goto err_disable_clk;
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}
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ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs);
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if (ret || nr_outputs > WZRD_NUM_OUTPUTS) {
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ret = -EINVAL;
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goto err_disable_clk;
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}
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clkout_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_out0", dev_name(&pdev->dev));
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if (nr_outputs == 1) {
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clk_wzrd->clkout[0] = clk_wzrd_register_divider
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(&pdev->dev, clkout_name,
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__clk_get_name(clk_wzrd->clk_in1), 0,
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clk_wzrd->base, WZRD_CLK_CFG_REG(3),
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WZRD_CLKOUT_DIVIDE_SHIFT,
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WZRD_CLKOUT_DIVIDE_WIDTH,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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DIV_ALL, &clkwzrd_lock);
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goto out;
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}
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reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(0));
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reg_f = reg & WZRD_CLKFBOUT_FRAC_MASK;
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reg_f = reg_f >> WZRD_CLKFBOUT_FRAC_SHIFT;
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reg = reg & WZRD_CLKFBOUT_MULT_MASK;
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reg = reg >> WZRD_CLKFBOUT_MULT_SHIFT;
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mult = (reg * 1000) + reg_f;
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clk_name = kasprintf(GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
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clk_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_mul", dev_name(&pdev->dev));
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if (!clk_name) {
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ret = -ENOMEM;
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goto err_disable_clk;
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}
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ret = of_property_read_u32(np, "xlnx,nr-outputs", &nr_outputs);
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if (ret || nr_outputs > WZRD_NUM_OUTPUTS) {
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ret = -EINVAL;
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goto err_disable_clk;
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}
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if (nr_outputs == 1)
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flags = CLK_SET_RATE_PARENT;
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clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor
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(&pdev->dev, clk_name,
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__clk_get_name(clk_wzrd->clk_in1),
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goto err_disable_clk;
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}
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clk_name = kasprintf(GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
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clk_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_mul_div", dev_name(&pdev->dev));
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if (!clk_name) {
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ret = -ENOMEM;
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goto err_rm_int_clk;
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@ -521,9 +704,8 @@ static int clk_wzrd_probe(struct platform_device *pdev)
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/* register div per output */
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for (i = nr_outputs - 1; i >= 0 ; i--) {
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const char *clkout_name;
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clkout_name = kasprintf(GFP_KERNEL, "%s_out%d", dev_name(&pdev->dev), i);
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clkout_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
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"%s_out%d", dev_name(&pdev->dev), i);
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if (!clkout_name) {
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ret = -ENOMEM;
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goto err_rm_int_clk;
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@ -537,7 +719,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
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WZRD_CLKOUT_DIVIDE_SHIFT,
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WZRD_CLKOUT_DIVIDE_WIDTH,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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NULL, &clkwzrd_lock);
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DIV_O, &clkwzrd_lock);
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else
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clk_wzrd->clkout[i] = clk_wzrd_register_divider
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(&pdev->dev, clkout_name,
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@ -546,7 +728,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
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WZRD_CLKOUT_DIVIDE_SHIFT,
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WZRD_CLKOUT_DIVIDE_WIDTH,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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NULL, &clkwzrd_lock);
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DIV_O, &clkwzrd_lock);
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if (IS_ERR(clk_wzrd->clkout[i])) {
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int j;
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@ -559,8 +741,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
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}
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}
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kfree(clk_name);
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out:
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clk_wzrd->clk_data.clks = clk_wzrd->clkout;
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clk_wzrd->clk_data.clk_num = ARRAY_SIZE(clk_wzrd->clkout);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_wzrd->clk_data);
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@ -585,7 +766,6 @@ static int clk_wzrd_probe(struct platform_device *pdev)
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err_rm_int_clks:
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clk_unregister(clk_wzrd->clks_internal[1]);
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err_rm_int_clk:
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kfree(clk_name);
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clk_unregister(clk_wzrd->clks_internal[0]);
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err_disable_clk:
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clk_disable_unprepare(clk_wzrd->axi_clk);
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