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mmc: sdhci: fix ctrl_2 on super-speed selection
This patch fixes the HC ctrl_2 programming where, in case of SDR104 and HS200, we have to write 100b in the the UHS Mode bits. We wrote 101b that is reserved from Arasan Specs. Reported-by: Youssef Triki <youssef.triki@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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1 changed files with 3 additions and 4 deletions
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@ -1543,16 +1543,15 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/* Select Bus Speed Mode for host */
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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if (ios->timing == MMC_TIMING_MMC_HS200)
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ctrl_2 |= SDHCI_CTRL_HS_SDR200;
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if ((ios->timing == MMC_TIMING_MMC_HS200) ||
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(ios->timing == MMC_TIMING_UHS_SDR104))
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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else if (ios->timing == MMC_TIMING_UHS_SDR12)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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else if (ios->timing == MMC_TIMING_UHS_SDR25)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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else if (ios->timing == MMC_TIMING_UHS_SDR50)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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else if (ios->timing == MMC_TIMING_UHS_SDR104)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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else if (ios->timing == MMC_TIMING_UHS_DDR50)
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ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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