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drm/i915/display: Store compressed bpp in U6.4 format
DSC parameter bits_per_pixel is stored in U6.4 format. The 4 bits represent the fractional part of the bpp. Currently we use compressed_bpp member of dsc structure to store only the integral part of the bits_per_pixel. To store the full bits_per_pixel along with the fractional part, compressed_bpp is changed to store bpp in U6.4 formats. Intergral part is retrieved by simply right shifting the member compressed_bpp by 4. v2: -Use to_bpp_int, to_bpp_frac_dec, to_bpp_x16 helpers while dealing with compressed bpp. (Suraj) -Fix comment styling. (Suraj) v3: -Add separate file for 6.4 fixed point helper(Jani, Nikula) -Add comment for magic values(Suraj) v4: -Fix checkpatch warnings caused by renaming(Suraj) v5: -Rebase. -Use existing helpers for conversion of bpp_int to bpp_x16 and vice versa. Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Sui Jingfeng <suijingfeng@loongson.cn> Link: https://patchwork.freedesktop.org/patch/msgid/20231110101020.4067342-3-ankit.k.nautiyal@intel.com
This commit is contained in:
parent
0c2287c965
commit
59a266f068
10 changed files with 33 additions and 28 deletions
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@ -330,7 +330,7 @@ static int afe_clk(struct intel_encoder *encoder,
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int bpp;
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if (crtc_state->dsc.compression_enable)
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bpp = crtc_state->dsc.compressed_bpp;
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bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
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else
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bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
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@ -860,7 +860,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
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* compressed and non-compressed bpp.
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*/
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if (crtc_state->dsc.compression_enable) {
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mul = crtc_state->dsc.compressed_bpp;
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mul = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
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div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
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}
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@ -884,7 +884,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
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int bpp, line_time_us, byte_clk_period_ns;
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if (crtc_state->dsc.compression_enable)
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bpp = crtc_state->dsc.compressed_bpp;
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bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
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else
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bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
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@ -1451,8 +1451,8 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
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struct drm_display_mode *adjusted_mode =
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&pipe_config->hw.adjusted_mode;
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if (pipe_config->dsc.compressed_bpp) {
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int div = pipe_config->dsc.compressed_bpp;
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if (pipe_config->dsc.compressed_bpp_x16) {
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int div = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
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int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
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adjusted_mode->crtc_htotal =
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@ -528,7 +528,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
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h_active = crtc_state->hw.adjusted_mode.crtc_hdisplay;
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h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
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pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
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vdsc_bpp = crtc_state->dsc.compressed_bpp;
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vdsc_bpp = to_bpp_int(crtc_state->dsc.compressed_bpp_x16);
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cdclk = i915->display.cdclk.hw.cdclk;
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/* fec= 0.972261, using rounding multiplier of 1000000 */
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fec_coeff = 972261;
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@ -3414,8 +3414,8 @@ static void fill_dsc(struct intel_crtc_state *crtc_state,
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crtc_state->pipe_bpp = bpc * 3;
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crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp,
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VBT_DSC_MAX_BPP(dsc->max_bpp));
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crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp,
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VBT_DSC_MAX_BPP(dsc->max_bpp)));
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/*
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* FIXME: This is ugly, and slice count should take DSC engine
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@ -2598,8 +2598,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
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* => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
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*/
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int bigjoiner_interface_bits = DISPLAY_VER(i915) > 13 ? 36 : 24;
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int min_cdclk_bj = (crtc_state->dsc.compressed_bpp * pixel_clock) /
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(2 * bigjoiner_interface_bits);
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int min_cdclk_bj =
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(to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
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pixel_clock) / (2 * bigjoiner_interface_bits);
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min_cdclk = max(min_cdclk, min_cdclk_bj);
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}
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@ -5434,7 +5434,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
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PIPE_CONF_CHECK_I(dsc.compression_enable);
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PIPE_CONF_CHECK_I(dsc.dsc_split);
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PIPE_CONF_CHECK_I(dsc.compressed_bpp);
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PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
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PIPE_CONF_CHECK_BOOL(splitter.enable);
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PIPE_CONF_CHECK_I(splitter.link_count);
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@ -1363,7 +1363,8 @@ struct intel_crtc_state {
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struct {
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bool compression_enable;
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bool dsc_split;
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u16 compressed_bpp;
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/* Compressed Bpp in U6.4 format (first 4 bits for fractional part) */
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u16 compressed_bpp_x16;
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u8 slice_count;
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struct drm_dsc_config config;
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} dsc;
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@ -1885,7 +1885,8 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
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valid_dsc_bpp[i],
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timeslots);
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if (ret == 0) {
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pipe_config->dsc.compressed_bpp = valid_dsc_bpp[i];
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pipe_config->dsc.compressed_bpp_x16 =
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to_bpp_x16(valid_dsc_bpp[i]);
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return 0;
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}
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}
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@ -1923,7 +1924,8 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp,
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compressed_bpp,
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timeslots);
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if (ret == 0) {
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pipe_config->dsc.compressed_bpp = compressed_bpp;
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pipe_config->dsc.compressed_bpp_x16 =
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to_bpp_x16(compressed_bpp);
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return 0;
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}
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}
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@ -2120,7 +2122,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
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/* Compressed BPP should be less than the Input DSC bpp */
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dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
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pipe_config->dsc.compressed_bpp = max(dsc_min_bpp, dsc_max_bpp);
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pipe_config->dsc.compressed_bpp_x16 =
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to_bpp_x16(max(dsc_min_bpp, dsc_max_bpp));
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pipe_config->pipe_bpp = pipe_bpp;
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@ -2209,18 +2212,18 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
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ret = intel_dp_dsc_compute_params(connector, pipe_config);
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if (ret < 0) {
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drm_dbg_kms(&dev_priv->drm,
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"Cannot compute valid DSC parameters for Input Bpp = %d "
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"Compressed BPP = %d\n",
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"Cannot compute valid DSC parameters for Input Bpp = %d"
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"Compressed BPP = " BPP_X16_FMT "\n",
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pipe_config->pipe_bpp,
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pipe_config->dsc.compressed_bpp);
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BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
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return ret;
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}
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pipe_config->dsc.compression_enable = true;
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drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
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"Compressed Bpp = %d Slice Count = %d\n",
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"Compressed Bpp = " BPP_X16_FMT " Slice Count = %d\n",
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pipe_config->pipe_bpp,
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pipe_config->dsc.compressed_bpp,
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BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16),
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pipe_config->dsc.slice_count);
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return 0;
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@ -2393,15 +2396,15 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
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if (pipe_config->dsc.compression_enable) {
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drm_dbg_kms(&i915->drm,
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"DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
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"DP lane count %d clock %d Input bpp %d Compressed bpp " BPP_X16_FMT "\n",
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pipe_config->lane_count, pipe_config->port_clock,
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pipe_config->pipe_bpp,
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pipe_config->dsc.compressed_bpp);
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BPP_X16_ARGS(pipe_config->dsc.compressed_bpp_x16));
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drm_dbg_kms(&i915->drm,
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"DP link rate required %i available %i\n",
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intel_dp_link_required(adjusted_mode->crtc_clock,
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pipe_config->dsc.compressed_bpp),
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to_bpp_int_roundup(pipe_config->dsc.compressed_bpp_x16)),
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intel_dp_max_data_rate(pipe_config->port_clock,
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pipe_config->lane_count));
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} else {
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@ -2863,7 +2866,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
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drm_dp_enhanced_frame_cap(intel_dp->dpcd);
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if (pipe_config->dsc.compression_enable)
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link_bpp = pipe_config->dsc.compressed_bpp;
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link_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
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else
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link_bpp = intel_dp_output_bpp(pipe_config->output_format,
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pipe_config->pipe_bpp);
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@ -228,7 +228,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
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if (!dsc)
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crtc_state->pipe_bpp = bpp;
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else
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crtc_state->dsc.compressed_bpp = bpp;
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crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
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drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
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}
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@ -70,7 +70,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
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return PTR_ERR(crtc_state);
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if (crtc_state->dsc.compression_enable)
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link_bpp = crtc_state->dsc.compressed_bpp;
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link_bpp = crtc_state->dsc.compressed_bpp_x16;
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else
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/*
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* TODO: for YUV420 the actual link bpp is only half
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@ -248,7 +248,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
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struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
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u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
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u16 compressed_bpp = to_bpp_int(pipe_config->dsc.compressed_bpp_x16);
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int err;
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int ret;
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@ -874,7 +874,7 @@ static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
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if (vdsc_cfg->native_420)
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vdsc_cfg->bits_per_pixel >>= 1;
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crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
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crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
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/* PPS 2 */
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pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
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