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locking, x86: mce: Annotate cmci_discover_lock as raw
The cmci_discover_lock can be taken in atomic context (cpu bring up sequence) and therefore cannot be preempted on -rt. In mainline this change documents the low level nature of the lock - otherwise there's no functional difference. Lockdep and Sparse checking will work as usual. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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parent
e12f65f7a4
commit
59d958d2c7
1 changed files with 5 additions and 5 deletions
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@ -28,7 +28,7 @@ static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
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* cmci_discover_lock protects against parallel discovery attempts
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* which could race against each other.
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*/
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static DEFINE_SPINLOCK(cmci_discover_lock);
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static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
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#define CMCI_THRESHOLD 1
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@ -85,7 +85,7 @@ static void cmci_discover(int banks, int boot)
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int hdr = 0;
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int i;
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spin_lock_irqsave(&cmci_discover_lock, flags);
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raw_spin_lock_irqsave(&cmci_discover_lock, flags);
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for (i = 0; i < banks; i++) {
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u64 val;
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@ -116,7 +116,7 @@ static void cmci_discover(int banks, int boot)
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WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
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}
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}
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spin_unlock_irqrestore(&cmci_discover_lock, flags);
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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if (hdr)
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printk(KERN_CONT "\n");
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}
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@ -150,7 +150,7 @@ void cmci_clear(void)
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if (!cmci_supported(&banks))
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return;
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spin_lock_irqsave(&cmci_discover_lock, flags);
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raw_spin_lock_irqsave(&cmci_discover_lock, flags);
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for (i = 0; i < banks; i++) {
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if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
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continue;
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@ -160,7 +160,7 @@ void cmci_clear(void)
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wrmsrl(MSR_IA32_MCx_CTL2(i), val);
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__clear_bit(i, __get_cpu_var(mce_banks_owned));
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}
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spin_unlock_irqrestore(&cmci_discover_lock, flags);
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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}
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/*
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