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net/mlx4_core: Port aggregation low level interface
Implement the hardware interface required for port aggregation. 1. Disable RX port check on receive - don't perform a validity check that matches to QP's port and the port where the packet is received. 2. Virtual to physical port remap - configure virtual to physical port mapping. Port remap capability for virtual functions. Signed-off-by: Moni Shoua <monis@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
69e6113343
commit
59e14e3250
5 changed files with 77 additions and 6 deletions
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@ -1583,6 +1583,15 @@ static struct mlx4_cmd_info cmd_info[] = {
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.verify = NULL,
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.wrapper = mlx4_CMD_EPERM_wrapper
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},
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{
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.opcode = MLX4_CMD_VIRT_PORT_MAP,
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.has_inbox = false,
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.has_outbox = false,
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.out_is_imm = false,
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.encode_slave_id = false,
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.verify = NULL,
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.wrapper = mlx4_CMD_EPERM_wrapper
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},
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};
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static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
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@ -142,7 +142,8 @@ static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
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[17] = "Asymmetric EQs support",
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[18] = "More than 80 VFs support",
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[19] = "Performance optimized for limited rule configuration flow steering support",
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[20] = "Recoverable error events support"
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[20] = "Recoverable error events support",
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[21] = "Port Remap support"
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};
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int i;
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@ -863,6 +864,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
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MLX4_GET(dev_cap->bmme_flags, outbox,
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QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
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if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
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if (field & 0x20)
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dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
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@ -1120,9 +1123,10 @@ int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
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field &= 0x7f;
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MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
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/* For guests, disable mw type 2 */
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/* For guests, disable mw type 2 and port remap*/
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MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
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bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
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bmme_flags &= ~MLX4_FLAG_PORT_REMAP;
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MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
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/* turn off device-managed steering capability if not enabled */
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@ -2100,13 +2104,16 @@ struct mlx4_config_dev {
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__be32 rsvd1[3];
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__be16 vxlan_udp_dport;
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__be16 rsvd2;
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__be32 rsvd3[27];
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__be16 rsvd4;
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u8 rsvd5;
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__be32 rsvd3;
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__be32 roce_flags;
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__be32 rsvd4[25];
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__be16 rsvd5;
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u8 rsvd6;
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u8 rx_checksum_val;
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};
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#define MLX4_VXLAN_UDP_DPORT (1 << 0)
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#define MLX4_DISABLE_RX_PORT BIT(18)
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static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
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{
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@ -2209,6 +2216,45 @@ int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
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}
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EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
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#define CONFIG_DISABLE_RX_PORT BIT(15)
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int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis)
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{
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struct mlx4_config_dev config_dev;
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memset(&config_dev, 0, sizeof(config_dev));
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config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT);
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if (dis)
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config_dev.roce_flags =
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cpu_to_be32(CONFIG_DISABLE_RX_PORT);
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return mlx4_CONFIG_DEV_set(dev, &config_dev);
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}
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int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2)
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{
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struct mlx4_cmd_mailbox *mailbox;
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struct {
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__be32 v_port1;
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__be32 v_port2;
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} *v2p;
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int err;
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return -ENOMEM;
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v2p = mailbox->buf;
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v2p->v_port1 = cpu_to_be32(port1);
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v2p->v_port2 = cpu_to_be32(port2);
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err = mlx4_cmd(dev, mailbox->dma, 0,
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MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP,
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MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
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mlx4_free_cmd_mailbox(dev, mailbox);
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return err;
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}
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int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
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{
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@ -71,6 +71,7 @@ enum {
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/*master notify fw on finish for slave's flr*/
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MLX4_CMD_INFORM_FLR_DONE = 0x5b,
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MLX4_CMD_VIRT_PORT_MAP = 0x5c,
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MLX4_CMD_GET_OP_REQ = 0x59,
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/* TPT commands */
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@ -170,6 +171,12 @@ enum {
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MLX4_CMD_TIME_CLASS_C = 60000,
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};
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enum {
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/* virtual to physical port mapping opcode modifiers */
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MLX4_GET_PORT_VIRT2PHY = 0x0,
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MLX4_SET_PORT_VIRT2PHY = 0x1,
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};
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enum {
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MLX4_MAILBOX_SIZE = 4096,
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MLX4_ACCESS_MEM_ALIGN = 256,
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@ -201,7 +201,8 @@ enum {
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MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 17,
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MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
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MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19,
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MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20
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MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20,
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MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21
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};
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enum {
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@ -253,9 +254,14 @@ enum {
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MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
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MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
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MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
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MLX4_BMME_FLAG_PORT_REMAP = 1 << 24,
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MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28,
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};
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enum {
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MLX4_FLAG_PORT_REMAP = MLX4_BMME_FLAG_PORT_REMAP
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};
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enum mlx4_event {
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MLX4_EVENT_TYPE_COMP = 0x00,
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MLX4_EVENT_TYPE_PATH_MIG = 0x01,
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@ -1378,6 +1384,8 @@ int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port);
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int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port);
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int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port);
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int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis);
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int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2);
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int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port);
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int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port);
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int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
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@ -96,6 +96,7 @@ enum {
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MLX4_QP_BIT_RRE = 1 << 15,
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MLX4_QP_BIT_RWE = 1 << 14,
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MLX4_QP_BIT_RAE = 1 << 13,
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MLX4_QP_BIT_FPP = 1 << 3,
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MLX4_QP_BIT_RIC = 1 << 4,
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};
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