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drm/amd/pp: Move DPMTABLE_* definitions to common header file
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ee85c07abe
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59fc8cde73
3 changed files with 11 additions and 11 deletions
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@ -34,11 +34,6 @@
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#define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2
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#define SMU7_VOLTAGE_CONTROL_MERGED 0x3
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#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
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#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
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#define DPMTABLE_UPDATE_SCLK 0x00000004
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#define DPMTABLE_UPDATE_MCLK 0x00000008
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enum gpu_pt_config_reg_type {
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GPU_CONFIGREG_MMR = 0,
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GPU_CONFIGREG_SMC_IND,
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@ -189,12 +189,6 @@ struct vega10_vbios_boot_state {
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uint32_t dcef_clock;
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};
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#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
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#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
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#define DPMTABLE_UPDATE_SCLK 0x00000004
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#define DPMTABLE_UPDATE_MCLK 0x00000008
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#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
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struct vega10_smc_state_table {
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uint32_t soc_boot_level;
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uint32_t gfx_boot_level;
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@ -358,6 +358,17 @@ struct phm_clocks {
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uint32_t clock[MAX_NUM_CLOCKS];
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};
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#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
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#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
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#define DPMTABLE_UPDATE_SCLK 0x00000004
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#define DPMTABLE_UPDATE_MCLK 0x00000008
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#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
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/* To determine if sclk and mclk are in overdrive state */
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#define SCLK_OVERDRIVE_ENABLED 0x00000001
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#define MCLK_OVERDRIVE_ENABLED 0x00000002
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#define VDDC_OVERDRIVE_ENABLED 0x00000010
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struct phm_odn_performance_level {
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uint32_t clock;
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uint32_t vddc;
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