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drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none of these workarounds are actually tied to MTL as a platform; they only relate to the Xe_LPG graphics IP, regardless of what platform it appears in. At the moment MTL is the only platform that uses Xe_LPG with IP versions 12.70 and 12.71, but we can't count on this being true in the future. Switch these to use a new IS_GFX_GT_IP_STEP() macro instead that is purely based on IP version. IS_GFX_GT_IP_STEP() is also GT-based rather than device-based, which will help prevent mistakes where we accidentally try to apply Xe_LPG graphics workarounds to the Xe_LPM+ media GT and vice-versa. v2: - Switch to a more generic and shorter IS_GT_IP_STEP macro that can be used for both graphics and media IP (and any other kind of GTs that show up in the future). v3: - Switch back to long-form IS_GFX_GT_IP_STEP macro. (Jani) - Move macro to intel_gt.h. (Andi) v4: - Build IS_GFX_GT_IP_STEP on top of IS_GFX_GT_IP_RANGE and IS_GRAPHICS_STEP building blocks and name the parameters from/until rather than begin/fixed. (Jani) - Fix usage examples in comment. v5: - Tweak comment on macro. (Gustavo) Cc: Gustavo Sousa <gustavo.sousa@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-15-matthew.d.roper@intel.com
This commit is contained in:
parent
f7696ded7c
commit
5a213086a0
10 changed files with 62 additions and 43 deletions
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@ -20,6 +20,7 @@
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#include "skl_scaler.h"
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#include "skl_universal_plane.h"
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#include "skl_watermark.h"
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#include "gt/intel_gt.h"
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#include "pxp/intel_pxp.h"
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static const u32 skl_plane_formats[] = {
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@ -2169,8 +2170,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
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enum pipe pipe, enum plane_id plane_id)
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{
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/* Wa_14017240301 */
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
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if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
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return false;
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/* Wa_22011186057 */
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@ -4,9 +4,9 @@
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*/
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#include "gen8_engine_cs.h"
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#include "i915_drv.h"
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#include "intel_engine_regs.h"
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#include "intel_gpu_commands.h"
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#include "intel_gt.h"
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#include "intel_lrc.h"
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#include "intel_ring.h"
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@ -226,8 +226,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
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static int mtl_dummy_pipe_control(struct i915_request *rq)
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{
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/* Wa_14016712196 */
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if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
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if (IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
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u32 *cs;
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/* dummy PIPE_CONTROL + depth flush */
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@ -799,6 +799,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
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u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
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{
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struct drm_i915_private *i915 = rq->i915;
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struct intel_gt *gt = rq->engine->gt;
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u32 flags = (PIPE_CONTROL_CS_STALL |
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PIPE_CONTROL_TLB_INVALIDATE |
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PIPE_CONTROL_TILE_CACHE_FLUSH |
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@ -809,8 +810,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
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PIPE_CONTROL_FLUSH_ENABLE);
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/* Wa_14016712196 */
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
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/* dummy PIPE_CONTROL + depth flush */
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cs = gen12_emit_pipe_control(cs, 0,
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PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
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@ -25,6 +25,26 @@ struct drm_printer;
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GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
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GRAPHICS_VER_FULL((gt)->i915) <= (until)))
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/*
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* Check that the GT is a graphics GT with a specific IP version and has
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* a stepping in the range [from, until). The lower stepping bound is
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* inclusive, the upper bound is exclusive. The most common use-case of this
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* macro is for checking bounds for workarounds, which usually have a stepping
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* ("from") at which the hardware issue is first present and another stepping
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* ("until") at which a hardware fix is present and the software workaround is
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* no longer necessary. E.g.,
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*
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* IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)
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* IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B1, STEP_FOREVER)
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*
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* "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
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* stepping bound for the specified IP version.
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*/
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#define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \
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BUILD_BUG_ON_ZERO((until) <= (from)) + \
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(IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
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IS_GRAPHICS_STEP((gt)->i915, (from), (until))))
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#define GT_TRACE(gt, fmt, ...) do { \
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const struct intel_gt *gt__ __maybe_unused = (gt); \
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GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
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@ -3,8 +3,7 @@
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* Copyright © 2022 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_gt.h"
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#include "intel_gt_mcr.h"
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#include "intel_gt_print.h"
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#include "intel_gt_regs.h"
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@ -166,8 +165,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
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gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
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} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
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/* Wa_14016747170 */
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
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fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
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intel_uncore_read(gt->uncore,
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MTL_GT_ACTIVITY_FACTOR));
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@ -1346,8 +1346,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
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cs = gen12_emit_aux_table_inv(ce->engine, cs);
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/* Wa_16014892111 */
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if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
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if (IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
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IS_DG2(ce->engine->i915))
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cs = dg2_emit_draw_watermark_setting(cs);
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@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
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if (GRAPHICS_VER(gt->i915) < 11)
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return false;
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if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
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return true;
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if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
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@ -781,24 +781,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
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static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
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struct i915_wa_list *wal)
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{
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struct drm_i915_private *i915 = engine->i915;
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struct intel_gt *gt = engine->gt;
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dg2_ctx_gt_tuning_init(engine, wal);
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
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wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
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}
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static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
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struct i915_wa_list *wal)
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{
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struct drm_i915_private *i915 = engine->i915;
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struct intel_gt *gt = engine->gt;
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xelpg_ctx_gt_tuning_init(engine, wal);
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
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/* Wa_14014947963 */
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wa_masked_field_set(wal, VF_PREEMPTION,
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PREEMPTION_VERTEX_COUNT, 0x4000);
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/* Wa_22016670082 */
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wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
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if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
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/* Wa_14014830051 */
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wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
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rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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{
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struct drm_i915_private *i915 = engine->i915;
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struct intel_gt *gt = engine->gt;
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
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/* Wa_22014600077 */
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wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
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ENABLE_EU_COUNT_FOR_TDL_FLUSH);
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}
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
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IS_DG2(i915)) {
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/* Wa_1509727124 */
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wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
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SC_DISABLE_POWER_OPTIMIZATION_EBB);
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}
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_DG2(i915)) {
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/* Wa_22012856258 */
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wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
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general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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{
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struct drm_i915_private *i915 = engine->i915;
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struct intel_gt *gt = engine->gt;
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add_render_compute_tuning_settings(engine->gt, wal);
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add_render_compute_tuning_settings(gt, wal);
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if (GRAPHICS_VER(i915) >= 11) {
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/* This is not a Wa (although referred to as
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@ -2847,13 +2849,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
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GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
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}
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
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/* Wa_14017856879 */
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wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
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/*
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* Wa_14017066071
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* Wa_14017654203
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wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
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MTL_DISABLE_SAMPLER_SC_OOO);
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if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
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/* Wa_22015279794 */
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wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
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DISABLE_PREFETCH_INTO_IC);
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
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IS_DG2(i915)) {
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/* Wa_22013037850 */
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wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
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wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
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}
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if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
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IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
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IS_PONTEVECCHIO(i915) ||
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IS_DG2(i915)) {
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/* Wa_22014226127 */
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@ -273,7 +273,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
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flags |= GUC_WA_POLLCS;
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/* Wa_14014475959 */
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if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_DG2(gt->i915))
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flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
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@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
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/* Wa_14014475959:dg2 */
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if (engine->class == COMPUTE_CLASS)
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if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
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if (IS_GFX_GT_IP_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_DG2(engine->i915))
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engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
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@ -686,10 +686,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
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(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
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#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
|
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(IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
|
||||
IS_GRAPHICS_STEP(__i915, since, until))
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||||
|
||||
#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
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||||
(IS_METEORLAKE(__i915) && \
|
||||
IS_DISPLAY_STEP(__i915, since, until))
|
||||
|
|
Loading…
Reference in a new issue