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habanalabs/gaudi: fetch HBM ecc info from FW
Once FW security is enabled there is no access to HBM ecc registers, need to read values from FW using a dedicated interface. Signed-off-by: Ofir Bitton <obitton@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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parent
d611b9f0b1
commit
5a2998f46c
2 changed files with 72 additions and 7 deletions
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@ -6839,10 +6839,41 @@ static int gaudi_soft_reset_late_init(struct hl_device *hdev)
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return hl_fw_unmask_irq_arr(hdev, gaudi->events, sizeof(gaudi->events));
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}
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static int gaudi_hbm_read_interrupts(struct hl_device *hdev, int device)
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static int gaudi_hbm_read_interrupts(struct hl_device *hdev, int device,
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struct hl_eq_hbm_ecc_data *hbm_ecc_data)
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{
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int ch, err = 0;
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u32 base, val, val2;
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u32 base, val, val2, wr_par, rd_par, ca_par, derr, serr, type, ch;
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int err = 0;
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if (!hdev->asic_prop.fw_security_disabled) {
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if (!hbm_ecc_data) {
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dev_err(hdev->dev, "No FW ECC data");
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return 0;
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}
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wr_par = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK,
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le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
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rd_par = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK,
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le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
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ca_par = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK,
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le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
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derr = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_DERR_MASK,
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le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
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serr = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_SERR_MASK,
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le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
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type = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK,
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le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
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ch = FIELD_GET(CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK,
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le32_to_cpu(hbm_ecc_data->hbm_ecc_info));
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dev_err(hdev->dev,
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"HBM%d pc%d interrupts info: WR_PAR=%d, RD_PAR=%d, CA_PAR=%d, SERR=%d, DERR=%d\n",
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device, ch, wr_par, rd_par, ca_par, serr, derr);
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err = 1;
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return 0;
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}
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base = GAUDI_HBM_CFG_BASE + device * GAUDI_HBM_CFG_OFFSET;
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for (ch = 0 ; ch < GAUDI_HBM_CHANNELS ; ch++) {
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@ -6858,7 +6889,7 @@ static int gaudi_hbm_read_interrupts(struct hl_device *hdev, int device)
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val2 = RREG32(base + ch * 0x1000 + 0x060);
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dev_err(hdev->dev,
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"HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DED_CNT=%d\n",
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"HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DEC_CNT=%d\n",
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device, ch * 2,
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RREG32(base + ch * 0x1000 + 0x064),
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(val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10,
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@ -6878,7 +6909,7 @@ static int gaudi_hbm_read_interrupts(struct hl_device *hdev, int device)
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val2 = RREG32(base + ch * 0x1000 + 0x070);
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dev_err(hdev->dev,
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"HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DED_CNT=%d\n",
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"HBM%d pc%d ECC info: 1ST_ERR_ADDR=0x%x, 1ST_ERR_TYPE=%d, SEC_CONT_CNT=%d, SEC_CNT=%d, DEC_CNT=%d\n",
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device, ch * 2 + 1,
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RREG32(base + ch * 0x1000 + 0x074),
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(val2 & 0x200) >> 9, (val2 & 0xFC00) >> 10,
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@ -7079,7 +7110,8 @@ static void gaudi_handle_eqe(struct hl_device *hdev,
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case GAUDI_EVENT_HBM3_SPI_0:
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gaudi_print_irq_info(hdev, event_type, false);
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gaudi_hbm_read_interrupts(hdev,
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gaudi_hbm_event_to_dev(event_type));
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gaudi_hbm_event_to_dev(event_type),
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&eq_entry->hbm_ecc_data);
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if (hdev->hard_reset_on_fw_events)
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hl_device_reset(hdev, true, false);
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break;
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@ -7090,7 +7122,8 @@ static void gaudi_handle_eqe(struct hl_device *hdev,
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case GAUDI_EVENT_HBM3_SPI_1:
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gaudi_print_irq_info(hdev, event_type, false);
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gaudi_hbm_read_interrupts(hdev,
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gaudi_hbm_event_to_dev(event_type));
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gaudi_hbm_event_to_dev(event_type),
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&eq_entry->hbm_ecc_data);
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break;
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case GAUDI_EVENT_TPC0_DEC:
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@ -11,6 +11,37 @@
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#include <linux/types.h>
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#include <linux/if_ether.h>
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#define NUM_HBM_PSEUDO_CH 2
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#define NUM_HBM_CH_PER_DEV 8
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#define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0
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#define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001
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#define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1
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#define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002
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#define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2
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#define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004
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#define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3
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#define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008
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#define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4
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#define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010
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#define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5
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#define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020
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#define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6
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#define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0
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struct hl_eq_hbm_ecc_data {
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/* SERR counter */
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__le32 sec_cnt;
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/* DERR counter */
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__le32 dec_cnt;
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/* Supplemental Information according to the mask bits */
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__le32 hbm_ecc_info;
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/* Address in hbm where the ecc happened */
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__le32 first_addr;
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/* SERR continuous address counter */
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__le32 sec_cont_cnt;
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__le32 pad;
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};
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/*
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* EVENT QUEUE
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*/
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@ -31,6 +62,7 @@ struct hl_eq_entry {
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struct hl_eq_header hdr;
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union {
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struct hl_eq_ecc_data ecc_data;
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struct hl_eq_hbm_ecc_data hbm_ecc_data;
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__le64 data[7];
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};
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};
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