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clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
[ Upstream commitf12d028b74
] Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate computed in sam9x60_frac_pll_recalc_rate() and the one computed in sam9x60_frac_pll_compute_mul_frac(). Fixes:43b1bb4a9b
("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20211011112719.3951784-8-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 2 additions and 2 deletions
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@ -71,8 +71,8 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
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struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
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struct sam9x60_frac *frac = to_sam9x60_frac(core);
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return (parent_rate * (frac->mul + 1) +
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((u64)parent_rate * frac->frac >> 22));
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return parent_rate * (frac->mul + 1) +
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DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
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}
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static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
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