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accel/habanalabs/gaudi2: un-secure register for engine cores interrupt
The F/W dynamically allocates one of the PSOC scratchpad registers for the engine cores, so they can raise events towards the F/W. To allow the engine cores to access this register, this register must be non-secured. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
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1 changed files with 17 additions and 3 deletions
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@ -2907,7 +2907,7 @@ static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)
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* - range 11: NIC11_CFG + *_DBG (not including TPC_DBG)
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*
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* If F/W security is not enabled:
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* - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP)
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* - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP, PSOC_EFUSE and PSOC_GLOBAL_CONF)
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*/
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u64 lbw_range_min_short[] = {
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mmNIC0_TX_AXUSER_BASE,
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@ -2923,7 +2923,7 @@ static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)
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mmNIC10_TX_AXUSER_BASE,
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mmNIC11_TX_AXUSER_BASE,
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mmPSOC_I2C_M0_BASE,
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mmPSOC_EFUSE_BASE
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mmPSOC_GPIO0_BASE
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};
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u64 lbw_range_max_short[] = {
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mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
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@ -3219,6 +3219,7 @@ static void gaudi2_init_range_registers(struct hl_device *hdev)
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*/
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static int gaudi2_init_protection_bits(struct hl_device *hdev)
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{
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u32 *user_regs_array = NULL, user_regs_array_size = 0, engine_core_intr_reg;
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u32 instance_offset;
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int rc = 0;
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@ -3389,11 +3390,24 @@ static int gaudi2_init_protection_bits(struct hl_device *hdev)
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/* PSOC.
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* Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
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* protected by privileged RR.
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* For PSOC_GLOBAL_CONF, need to un-secure the scratchpad register which is used for engine
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* cores to raise events towards F/W.
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*/
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engine_core_intr_reg = (u32) (hdev->asic_prop.engine_core_interrupt_reg_addr - CFG_BASE);
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if (engine_core_intr_reg >= mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 &&
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engine_core_intr_reg <= mmPSOC_GLOBAL_CONF_SCRATCHPAD_31) {
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user_regs_array = &engine_core_intr_reg;
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user_regs_array_size = 1;
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} else {
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dev_err(hdev->dev,
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"Engine cores register for interrupts (%#x) is not a PSOC scratchpad register\n",
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engine_core_intr_reg);
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}
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rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
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HL_PB_SINGLE_INSTANCE, HL_PB_NA,
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gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf),
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NULL, HL_PB_NA);
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user_regs_array, user_regs_array_size);
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if (!hdev->asic_prop.fw_security_enabled)
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rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
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