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drm/i915/dvo: Define a few more DVO register bits

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Define a few extra interrupt related bits on the DVO register.
One of these we included in the DVO_PRESERVE_MASK already.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221122120825.26338-6-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Ville Syrjälä 2022-11-22 14:08:20 +02:00
parent a8d9a13d24
commit 5abd7d8d0e
2 changed files with 5 additions and 2 deletions
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3
drivers/gpu/drm/i915/display/intel_dvo.c
View file

@ -290,7 +290,8 @@ static void intel_dvo_pre_enable(struct intel_atomic_state *state,
/* Save the data order, since I don't know what it should be set to. */
dvo_val = intel_de_read(i915, DVO(port)) &
(DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
(DVO_DEDICATED_INT_ENABLE |
DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
DVO_BLANK_ACTIVE_HIGH;

4
drivers/gpu/drm/i915/i915_reg.h
View file

@ -2602,6 +2602,9 @@
#define DVO_PIPE_STALL (1 << 28)
#define DVO_PIPE_STALL_TV (2 << 28)
#define DVO_PIPE_STALL_MASK (3 << 28)
#define DVO_INTERRUPT_SELECT (1 << 27)
#define DVO_DEDICATED_INT_ENABLE (1 << 26)
#define DVO_PRESERVE_MASK (0x3 << 24)
#define DVO_USE_VGA_SYNC (1 << 15)
#define DVO_DATA_ORDER_I740 (0 << 14)
#define DVO_DATA_ORDER_FP (1 << 14)
@ -2619,7 +2622,6 @@
#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
#define DVO_PRESERVE_MASK (0x7 << 24)
#define _DVOA_SRCDIM 0x61124
#define _DVOB_SRCDIM 0x61144
#define _DVOC_SRCDIM 0x61164