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ARM: cache-v7: use movw/movt instructions
We always build cache-v7.S for ARMv7, so we can use the ARMv7 16-bit move instructions to load large constants, rather than using constants in a literal pool. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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89c6bc5884
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1 changed files with 6 additions and 5 deletions
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@ -36,10 +36,10 @@ ENTRY(v7_invalidate_l1)
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mcr p15, 2, r0, c0, c0, 0
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mcr p15, 2, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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mrc p15, 1, r0, c0, c0, 0
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ldr r1, =0x7fff
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movw r1, #0x7fff
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and r2, r1, r0, lsr #13
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and r2, r1, r0, lsr #13
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ldr r1, =0x3ff
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movw r1, #0x3ff
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and r3, r1, r0, lsr #3 @ NumWays - 1
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and r3, r1, r0, lsr #3 @ NumWays - 1
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add r2, r2, #1 @ NumSets
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add r2, r2, #1 @ NumSets
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@ -95,7 +95,8 @@ ENTRY(v7_flush_dcache_louis)
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#ifdef CONFIG_ARM_ERRATA_643719
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#ifdef CONFIG_ARM_ERRATA_643719
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ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register
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ALT_SMP(mrceq p15, 0, r2, c0, c0, 0) @ read main ID register
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ALT_UP(reteq lr) @ LoUU is zero, so nothing to do
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ALT_UP(reteq lr) @ LoUU is zero, so nothing to do
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ldreq r1, =0x410fc090 @ ID of ARM Cortex A9 r0p?
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movweq r1, #:lower16:0x410fc090 @ ID of ARM Cortex A9 r0p?
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movteq r1, #:upper16:0x410fc090
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biceq r2, r2, #0x0000000f @ clear minor revision number
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biceq r2, r2, #0x0000000f @ clear minor revision number
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teqeq r2, r1 @ test for errata affected core and if so...
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teqeq r2, r1 @ test for errata affected core and if so...
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orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne')
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orreqs r3, #(1 << 21) @ fix LoUIS value (and set flags state to 'ne')
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@ -140,10 +141,10 @@ flush_levels:
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#endif
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#endif
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and r2, r1, #7 @ extract the length of the cache lines
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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movw r4, #0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff
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movw r7, #0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop1:
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loop1:
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mov r9, r7 @ create working copy of max index
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mov r9, r7 @ create working copy of max index
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