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ASoC: Intel: avs: TGL-based platforms support 

Define handlers specific to cAVS 2.5 platforms, that is TGL, ADL, RPL
and all other variants based on this very version of AudioDSP
architecture. Most operations are inherited from their predecessors with
the major difference being AudioDSP cores management - firmware handlers
that on its own so there is no need to interfere.

Reviewed-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://msgid.link/r/20240220115035.770402-9-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Cezary Rojewski 2024-02-20 12:50:33 +01:00 committed by Mark Brown
parent 275b583d04
commit 5acb19ecd1
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
4 changed files with 90 additions and 1 deletions
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2
sound/soc/intel/avs/Makefile
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@ -3,7 +3,7 @@
snd-soc-avs-objs := dsp.o ipc.o messages.o utils.o core.o loader.o \
topology.o path.o pcm.o board_selection.o control.o
snd-soc-avs-objs += cldma.o
snd-soc-avs-objs += skl.o apl.o cnl.o icl.o
snd-soc-avs-objs += skl.o apl.o cnl.o icl.o tgl.o
snd-soc-avs-objs += trace.o
# tell define_trace.h where to find the trace header

1
sound/soc/intel/avs/avs.h
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@ -68,6 +68,7 @@ extern const struct avs_dsp_ops avs_skl_dsp_ops;
extern const struct avs_dsp_ops avs_apl_dsp_ops;
extern const struct avs_dsp_ops avs_cnl_dsp_ops;
extern const struct avs_dsp_ops avs_icl_dsp_ops;
extern const struct avs_dsp_ops avs_tgl_dsp_ops;
#define AVS_PLATATTR_CLDMA BIT_ULL(0)
#define AVS_PLATATTR_IMR BIT_ULL(1)

34
sound/soc/intel/avs/core.c
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@ -828,6 +828,23 @@ static const struct avs_spec jsl_desc = {
.hipc = &cnl_hipc_spec,
};
#define AVS_TGL_BASED_SPEC(sname) \
static const struct avs_spec sname##_desc = { \
.name = #sname, \
.min_fw_version = { 10, 29, 0, 5646 }, \
.dsp_ops = &avs_tgl_dsp_ops, \
.core_init_mask = 1, \
.attributes = AVS_PLATATTR_IMR, \
.sram = &apl_sram_spec, \
.hipc = &cnl_hipc_spec, \
}
AVS_TGL_BASED_SPEC(lkf);
AVS_TGL_BASED_SPEC(tgl);
AVS_TGL_BASED_SPEC(ehl);
AVS_TGL_BASED_SPEC(adl);
AVS_TGL_BASED_SPEC(adl_n);
static const struct pci_device_id avs_ids[] = {
{ PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, &skl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_SKL, &skl_desc) },
@ -846,6 +863,23 @@ static const struct pci_device_id avs_ids[] = {
{ PCI_DEVICE_DATA(INTEL, HDA_ICL_N, &icl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ICL_H, &icl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_JSL_N, &jsl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_LKF, &lkf_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, &tgl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_TGL_H, &tgl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_CML_R, &tgl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_EHL_0, &ehl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_EHL_3, &ehl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_S, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_P, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_M, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_ADL_N, &adl_n_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_S, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_M, &adl_desc) },
{ PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, &adl_desc) },
{ 0 }
};
MODULE_DEVICE_TABLE(pci, avs_ids);

54
sound/soc/intel/avs/tgl.c Normal file
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@ -0,0 +1,54 @@
// SPDX-License-Identifier: GPL-2.0-only
//
// Copyright(c) 2021-2024 Intel Corporation. All rights reserved.
//
// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
// Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
//
#include "avs.h"
static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
{
core_mask &= AVS_MAIN_CORE_MASK;
if (!core_mask)
return 0;
return avs_dsp_core_power(adev, core_mask, power);
}
static int avs_tgl_dsp_core_reset(struct avs_dev *adev, u32 core_mask, bool reset)
{
core_mask &= AVS_MAIN_CORE_MASK;
if (!core_mask)
return 0;
return avs_dsp_core_reset(adev, core_mask, reset);
}
static int avs_tgl_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stall)
{
core_mask &= AVS_MAIN_CORE_MASK;
if (!core_mask)
return 0;
return avs_dsp_core_stall(adev, core_mask, stall);
}
const struct avs_dsp_ops avs_tgl_dsp_ops = {
.power = avs_tgl_dsp_core_power,
.reset = avs_tgl_dsp_core_reset,
.stall = avs_tgl_dsp_core_stall,
.irq_handler = avs_irq_handler,
.irq_thread = avs_cnl_irq_thread,
.int_control = avs_dsp_interrupt_control,
.load_basefw = avs_hda_load_basefw,
.load_lib = avs_hda_load_library,
.transfer_mods = avs_hda_transfer_modules,
.log_buffer_offset = avs_icl_log_buffer_offset,
.log_buffer_status = avs_apl_log_buffer_status,
.coredump = avs_apl_coredump,
.d0ix_toggle = avs_icl_d0ix_toggle,
.set_d0ix = avs_icl_set_d0ix,
AVS_SET_ENABLE_LOGS_OP(icl)
};