mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ARM: tegra: device tree changes
This branch contains all the changes to Tegra's device tree. The highlights are: * Many patches for Tegra124 SoC support, and the Venice2 board which uses that SoC. * Conversion to use more headers providing named constants for pinctrl and key codes, which improves readability. * A few cleanups. This branch is based on tag tegra-for-3.14-dmas-resets-rework in order to avoid conflicts with the DT changes required to use the common bindings for DMAs and resets. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSr3KtAAoJEMzrak5tbycxWpIP/A1zpgEBb8f0k/6aBRmiKisW G97QGbKVGL9ZJzi/CC12nD68URwN8mVfSRn9d+r7jN5zcEh+RAnCflj6LzX5c0nV XZndE9GnnpqpbsoWY+ubDPRvJnG2ZWPciMoR1p/ftNOHweELPG/5qTCoZLvi3abI 7L0EzMcNY6pC5RB0unCkTHWbmCsgTjDFQ0UI/iKJy+WYzSt0YLFW7TCMkEUBDfcg ElD2qhNYEZI5eRWO/ccl5lsoBwg47YSCXFti1rAZEyp7/SXRGm7gbdW0d/UpywoY 66V2GMP6mHeAMk6RFHSo1R2XGP5uxTY/n9UThtX5YuKTFYUwy541+xK4qWlVlpf+ SIukOFbHexPqvBbZWSB7lgdUemh2Cw/RTSDkp//hAHDcxMN5exjswgJIo9eIjzdi W78JaBZVBmsfJx+jEan6kNTV0TEbNLLnEhDdulLZjF2XxbGcWsYeJa3BmEGP8Lf1 VlzEOMXCkbar9kO8nJxCLXCK7JFR+GGZr2pF0hV9PIjrAao67INqDZpXvIZg5TnB aNoT+vzO19AoA7vj/aGmjVoahr/U3z+wFeHWoWyagq2Kxmx8RdYuV8IAo7CK9wo0 ok6J/MSdqq8WZYhIA/5BZffSl0RrlY2fHOpj3Jga72fjzgoH4BGmUQaWrHjQlzhh uqLwJymOSLsFIUD6itof =3M5I -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.14-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt From Stephen Warren: ARM: tegra: device tree changes This branch contains all the changes to Tegra's device tree. The highlights are: * Many patches for Tegra124 SoC support, and the Venice2 board which uses that SoC. * Conversion to use more headers providing named constants for pinctrl and key codes, which improves readability. * A few cleanups. This branch is based on tag tegra-for-3.14-dmas-resets-rework in order to avoid conflicts with the DT changes required to use the common bindings for DMAs and resets. * tag 'tegra-for-3.14-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits) ARM: tegra: Add SPI controller nodes for Tegra124 ARM: tegra: Fix misconfiguration of pin PH2 on Venice2 ARM: tegra: fix pinctrl misconfiguration on Venice2 ARM: tegra: add default pinctrl nodes for Venice2 ARM: tegra: correct Colibri T20 regulator settings ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl defines ARM: tegra: Add header file for pinctrl constants ARM: tegra: convert device tree files to use key defines ARM: tegra: Enable PWM on Venice2 ARM: tegra: Add Tegra124 PWM support ARM: tegra: add sound card to Venice2 DT ARM: tegra: add audio-related device to Tegra124 DT ARM: tegra: enable I2C controllers on Venice2 ARM: tegra: add I2C controllers to Tegra124 DT ARM: tegra: add MMC controllers to Tegra124 DT ARM: tegra: add Tegra124 pinmux node to DT ARM: tegra: add APB DMA controller to Tegra124 DT ARM: tegra: add reset properties to Tegra124 DTs ... Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
5aceaab397
24 changed files with 1931 additions and 1024 deletions
File diff suppressed because it is too large
Load diff
|
@ -1,5 +1,6 @@
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|||
#include <dt-bindings/clock/tegra114-car.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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@ -15,7 +16,7 @@ aliases {
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serial3 = &uartd;
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};
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gic: interrupt-controller {
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gic: interrupt-controller@50041000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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@ -39,14 +40,14 @@ timer@60005000 {
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clocks = <&tegra_car TEGRA114_CLK_TIMER>;
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};
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tegra_car: clock {
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tegra_car: clock@60006000 {
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compatible = "nvidia,tegra114-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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apbdma: dma {
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apbdma: dma@6000a000 {
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compatible = "nvidia,tegra114-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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@ -87,12 +88,12 @@ apbdma: dma {
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#dma-cells = <1>;
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};
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ahb: ahb {
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ahb: ahb@6000c004 {
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compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
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reg = <0x6000c004 0x14c>;
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};
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gpio: gpio {
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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@ -109,7 +110,7 @@ gpio: gpio {
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interrupt-controller;
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};
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pinmux: pinmux {
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pinmux: pinmux@70000868 {
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compatible = "nvidia,tegra114-pinmux";
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reg = <0x70000868 0x148 /* Pad control registers */
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0x70003000 0x40c>; /* Mux registers */
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@ -175,7 +176,7 @@ uartd: serial@70006300 {
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status = "disabled";
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};
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pwm: pwm {
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pwm: pwm@7000a000 {
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compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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@ -350,14 +351,14 @@ spi@7000de00 {
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status = "disabled";
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};
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rtc {
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rtc@7000e000 {
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compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA114_CLK_RTC>;
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};
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kbc {
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kbc@7000e200 {
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compatible = "nvidia,tegra114-kbc";
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reg = <0x7000e200 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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|
@ -367,14 +368,14 @@ kbc {
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status = "disabled";
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};
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pmc {
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pmc@7000e400 {
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compatible = "nvidia,tegra114-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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};
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iommu {
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iommu@70019010 {
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compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
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reg = <0x70019010 0x02c
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0x700191f0 0x010
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|
@ -385,7 +386,7 @@ iommu {
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nvidia,ahb = <&ahb>;
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};
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ahub {
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ahub@70080000 {
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compatible = "nvidia,tegra114-ahub";
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reg = <0x70080000 0x200>,
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<0x70080200 0x100>,
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||||
|
|
|
@ -10,10 +10,390 @@ memory {
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reg = <0x80000000 0x80000000>;
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};
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pinmux: pinmux@70000868 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_default>;
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pinmux_default: common {
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dap_mclk1_pw4 {
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nvidia,pins = "dap_mclk1_pw4";
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nvidia,function = "extperiph1";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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dap1_din_pn1 {
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nvidia,pins = "dap1_din_pn1",
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"dap1_dout_pn2",
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"dap1_fs_pn0",
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"dap1_sclk_pn3";
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nvidia,function = "i2s0";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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dap2_din_pa4 {
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nvidia,pins = "dap2_din_pa4",
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"dap2_dout_pa5",
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"dap2_fs_pa2",
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"dap2_sclk_pa3";
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nvidia,function = "i2s1";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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dvfs_pwm_px0 {
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nvidia,pins = "dvfs_pwm_px0";
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nvidia,function = "cldvfs";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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dvfs_clk_px2 {
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nvidia,pins = "dvfs_clk_px2";
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nvidia,function = "cldvfs";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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ulpi_clk_py0 {
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nvidia,pins = "ulpi_clk_py0",
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"ulpi_dir_py1",
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"ulpi_nxt_py2",
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"ulpi_stp_py3";
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nvidia,function = "spi1";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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cam_i2c_scl_pbb1 {
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nvidia,pins = "cam_i2c_scl_pbb1",
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"cam_i2c_sda_pbb2";
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nvidia,function = "i2c3";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,lock = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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gen2_i2c_scl_pt5 {
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nvidia,pins = "gen2_i2c_scl_pt5",
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"gen2_i2c_sda_pt6";
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nvidia,function = "i2c2";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,lock = <TEGRA_PIN_DISABLE>;
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nvidia,open-drain = <TEGRA_PIN_ENABLE>;
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};
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pg4 {
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nvidia,pins = "pg4",
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"pg5",
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"pg6",
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"pg7",
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"pi3";
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nvidia,function = "spi4";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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ph0 {
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nvidia,pins = "ph0";
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nvidia,function = "pwm0";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_ENABLE>;
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};
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ph1 {
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nvidia,pins = "ph1";
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nvidia,function = "pwm1";
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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};
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ph2 {
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nvidia,pins = "ph2";
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nvidia,function = "gmi";
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nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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};
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sdmmc1_clk_pz0 {
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nvidia,pins = "sdmmc1_clk_pz0",
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"sdmmc1_cmd_pz1",
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"sdmmc1_dat0_py7",
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"sdmmc1_dat1_py6",
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"sdmmc1_dat2_py5",
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"sdmmc1_dat3_py4";
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nvidia,function = "sdmmc1";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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||||
};
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sdmmc3_clk_pa6 {
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nvidia,pins = "sdmmc3_clk_pa6";
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nvidia,function = "sdmmc3";
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
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||||
};
|
||||
sdmmc3_cmd_pa7 {
|
||||
nvidia,pins = "sdmmc3_cmd_pa7",
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||||
"sdmmc3_dat0_pb7",
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||||
"sdmmc3_dat1_pb6",
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||||
"sdmmc3_dat2_pb5",
|
||||
"sdmmc3_dat3_pb4",
|
||||
"sdmmc3_clk_lb_out_pee4",
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"sdmmc3_clk_lb_in_pee5";
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||||
nvidia,function = "sdmmc3";
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||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_UP>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
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sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4";
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||||
nvidia,function = "sdmmc4";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc4_cmd_pt7 {
|
||||
nvidia,pins = "sdmmc4_cmd_pt7",
|
||||
"sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwr_i2c_scl_pz6 {
|
||||
nvidia,pins = "pwr_i2c_scl_pz6",
|
||||
"pwr_i2c_sda_pz7";
|
||||
nvidia,function = "i2cpwr";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
jtag_rtck {
|
||||
nvidia,pins = "jtag_rtck";
|
||||
nvidia,function = "rtck";
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
clk_32k_in {
|
||||
nvidia,pins = "clk_32k_in";
|
||||
nvidia,function = "clk";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
core_pwr_req {
|
||||
nvidia,pins = "core_pwr_req";
|
||||
nvidia,function = "pwron";
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
cpu_pwr_req {
|
||||
nvidia,pins = "cpu_pwr_req";
|
||||
nvidia,function = "cpu";
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwr_int_n {
|
||||
nvidia,pins = "pwr_int_n";
|
||||
nvidia,function = "pmi";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
reset_out_n {
|
||||
nvidia,pins = "reset_out_n";
|
||||
nvidia,function = "reset_out_n";
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
clk3_out_pee0 {
|
||||
nvidia,pins = "clk3_out_pee0";
|
||||
nvidia,function = "extperiph3";
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
dap4_din_pp5 {
|
||||
nvidia,pins = "dap4_din_pp5",
|
||||
"dap4_dout_pp6",
|
||||
"dap4_fs_pp4",
|
||||
"dap4_sclk_pp7";
|
||||
nvidia,function = "i2s3";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gen1_i2c_sda_pc5 {
|
||||
nvidia,pins = "gen1_i2c_sda_pc5",
|
||||
"gen1_i2c_scl_pc4";
|
||||
nvidia,function = "i2c1";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pu0 {
|
||||
nvidia,pins = "pu0",
|
||||
"pu1",
|
||||
"pu2",
|
||||
"pu3";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
uart2_cts_n_pj5 {
|
||||
nvidia,pins = "uart2_cts_n_pj5",
|
||||
"uart2_rts_n_pj6";
|
||||
nvidia,function = "uartb";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
uart2_rxd_pc3 {
|
||||
nvidia,pins = "uart2_rxd_pc3",
|
||||
"uart2_txd_pc2";
|
||||
nvidia,function = "irda";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
uart3_cts_n_pa1 {
|
||||
nvidia,pins = "uart3_cts_n_pa1",
|
||||
"uart3_rts_n_pc0",
|
||||
"uart3_rxd_pw7",
|
||||
"uart3_txd_pw6";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
hdmi_cec_pee3 {
|
||||
nvidia,pins = "hdmi_cec_pee3";
|
||||
nvidia,function = "cec";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ddc_scl_pv4 {
|
||||
nvidia,pins = "ddc_scl_pv4",
|
||||
"ddc_sda_pv5";
|
||||
nvidia,function = "i2c4";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
usb_vbus_en0_pn4 {
|
||||
nvidia,pins = "usb_vbus_en0_pn4";
|
||||
nvidia,function = "usb";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
usb_vbus_en1_pn5 {
|
||||
nvidia,pins = "usb_vbus_en1_pn5";
|
||||
nvidia,function = "usb";
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lock = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <32>;
|
||||
nvidia,pull-up-strength = <42>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
drive_sdio3 {
|
||||
nvidia,pins = "drive_sdio3";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <20>;
|
||||
nvidia,pull-up-strength = <36>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
drive_gma {
|
||||
nvidia,pins = "drive_gma";
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <1>;
|
||||
nvidia,pull-up-strength = <2>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,drive-type = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm: pwm@7000a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
acodec: audio-codec@10 {
|
||||
compatible = "maxim,max98090";
|
||||
reg = <0x10>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000c700 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
|
@ -24,4 +404,57 @@ pmc@7000e400 {
|
|||
nvidia,core-power-req-active-high;
|
||||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
sdhci@700b0400 {
|
||||
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
|
||||
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sdhci@700b0600 {
|
||||
status = "okay";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
ahub@70300000 {
|
||||
i2s@70301100 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-max98090-venice2",
|
||||
"nvidia,tegra-audio-max98090";
|
||||
nvidia,model = "NVIDIA Tegra Venice2";
|
||||
|
||||
nvidia,audio-routing =
|
||||
"Headphones", "HPR",
|
||||
"Headphones", "HPL",
|
||||
"Speakers", "SPKR",
|
||||
"Speakers", "SPKL",
|
||||
"Mic Jack", "MICBIAS",
|
||||
"IN34", "Mic Jack";
|
||||
|
||||
nvidia,i2s-controller = <&tegra_i2s1>;
|
||||
nvidia,audio-codec = <&acodec>;
|
||||
|
||||
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
|
||||
<&tegra_car TEGRA124_CLK_EXTERN1>;
|
||||
clock-names = "pll_a", "pll_a_out0", "mclk";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,4 +1,6 @@
|
|||
#include <dt-bindings/clock/tegra124-car.h>
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
@ -28,6 +30,14 @@ timer@60005000 {
|
|||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_TIMER>;
|
||||
};
|
||||
|
||||
tegra_car: clock@60006000 {
|
||||
compatible = "nvidia,tegra124-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpio: gpio@6000d000 {
|
||||
|
@ -47,6 +57,53 @@ gpio: gpio@6000d000 {
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
apbdma: dma@60020000 {
|
||||
compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
|
||||
reg = <0x60020000 0x1400>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
|
||||
resets = <&tegra_car 34>;
|
||||
reset-names = "dma";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pinmux: pinmux@70000868 {
|
||||
compatible = "nvidia,tegra124-pinmux";
|
||||
reg = <0x70000868 0x164>, /* Pad control registers */
|
||||
<0x70003000 0x434>; /* Mux registers */
|
||||
};
|
||||
|
||||
/*
|
||||
* There are two serial driver i.e. 8250 based simple serial
|
||||
* driver and APB DMA based serial driver for higher baudrate
|
||||
|
@ -60,6 +117,11 @@ serial@70006000 {
|
|||
reg = <0x70006000 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTA>;
|
||||
resets = <&tegra_car 6>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 8>, <&apbdma 8>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -68,6 +130,11 @@ serial@70006040 {
|
|||
reg = <0x70006040 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTB>;
|
||||
resets = <&tegra_car 7>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 9>, <&apbdma 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -76,6 +143,11 @@ serial@70006200 {
|
|||
reg = <0x70006200 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTC>;
|
||||
resets = <&tegra_car 55>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 10>, <&apbdma 10>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -84,6 +156,11 @@ serial@70006300 {
|
|||
reg = <0x70006300 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTD>;
|
||||
resets = <&tegra_car 65>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 19>, <&apbdma 19>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -92,6 +169,201 @@ serial@70006400 {
|
|||
reg = <0x70006400 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
|
||||
resets = <&tegra_car 66>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 20>, <&apbdma 20>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm@7000a000 {
|
||||
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_PWM>;
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x7000c000 0x100>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C1>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 12>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 21>, <&apbdma 21>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@7000c400 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x7000c400 0x100>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C2>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 54>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 22>, <&apbdma 22>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@7000c500 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x7000c500 0x100>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C3>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 67>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 23>, <&apbdma 23>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@7000c700 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x7000c700 0x100>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C4>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 103>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 26>, <&apbdma 26>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@7000d000 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x7000d000 0x100>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C5>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 47>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 24>, <&apbdma 24>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@7000d100 {
|
||||
compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
|
||||
reg = <0x7000d100 0x100>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2C6>;
|
||||
clock-names = "div-clk";
|
||||
resets = <&tegra_car 166>;
|
||||
reset-names = "i2c";
|
||||
dmas = <&apbdma 30>, <&apbdma 30>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d400 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x7000d400 0x200>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC1>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 41>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 15>, <&apbdma 15>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d600 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x7000d600 0x200>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC2>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 44>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 16>, <&apbdma 16>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000d800 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x7000d800 0x200>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC3>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 46>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 17>, <&apbdma 17>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000da00 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x7000da00 0x200>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC4>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 68>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 18>, <&apbdma 18>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000dc00 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x7000dc00 0x200>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC5>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 104>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 27>, <&apbdma 27>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi@7000de00 {
|
||||
compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
|
||||
reg = <0x7000de00 0x200>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SBC6>;
|
||||
clock-names = "spi";
|
||||
resets = <&tegra_car 105>;
|
||||
reset-names = "spi";
|
||||
dmas = <&apbdma 28>, <&apbdma 28>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -99,11 +371,157 @@ rtc@7000e000 {
|
|||
compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_RTC>;
|
||||
};
|
||||
|
||||
pmc@7000e400 {
|
||||
compatible = "nvidia,tegra124-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
sdhci@700b0000 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x700b0000 0x200>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
|
||||
resets = <&tegra_car 14>;
|
||||
reset-names = "sdhci";
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
sdhci@700b0200 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x700b0200 0x200>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
|
||||
resets = <&tegra_car 9>;
|
||||
reset-names = "sdhci";
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
sdhci@700b0400 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x700b0400 0x200>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
|
||||
resets = <&tegra_car 69>;
|
||||
reset-names = "sdhci";
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
sdhci@700b0600 {
|
||||
compatible = "nvidia,tegra124-sdhci";
|
||||
reg = <0x700b0600 0x200>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
|
||||
resets = <&tegra_car 15>;
|
||||
reset-names = "sdhci";
|
||||
status = "disable";
|
||||
};
|
||||
|
||||
ahub@70300000 {
|
||||
compatible = "nvidia,tegra124-ahub";
|
||||
reg = <0x70300000 0x200>,
|
||||
<0x70300800 0x800>,
|
||||
<0x70300200 0x600>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
|
||||
<&tegra_car TEGRA124_CLK_APBIF>;
|
||||
clock-names = "d_audio", "apbif";
|
||||
resets = <&tegra_car 106>, /* d_audio */
|
||||
<&tegra_car 107>, /* apbif */
|
||||
<&tegra_car 30>, /* i2s0 */
|
||||
<&tegra_car 11>, /* i2s1 */
|
||||
<&tegra_car 18>, /* i2s2 */
|
||||
<&tegra_car 101>, /* i2s3 */
|
||||
<&tegra_car 102>, /* i2s4 */
|
||||
<&tegra_car 108>, /* dam0 */
|
||||
<&tegra_car 109>, /* dam1 */
|
||||
<&tegra_car 110>, /* dam2 */
|
||||
<&tegra_car 10>, /* spdif */
|
||||
<&tegra_car 153>, /* amx */
|
||||
<&tegra_car 185>, /* amx1 */
|
||||
<&tegra_car 154>, /* adx */
|
||||
<&tegra_car 180>, /* adx1 */
|
||||
<&tegra_car 186>, /* afc0 */
|
||||
<&tegra_car 187>, /* afc1 */
|
||||
<&tegra_car 188>, /* afc2 */
|
||||
<&tegra_car 189>, /* afc3 */
|
||||
<&tegra_car 190>, /* afc4 */
|
||||
<&tegra_car 191>; /* afc5 */
|
||||
reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
|
||||
"i2s3", "i2s4", "dam0", "dam1", "dam2",
|
||||
"spdif", "amx", "amx1", "adx", "adx1",
|
||||
"afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
|
||||
dmas = <&apbdma 1>, <&apbdma 1>,
|
||||
<&apbdma 2>, <&apbdma 2>,
|
||||
<&apbdma 3>, <&apbdma 3>,
|
||||
<&apbdma 4>, <&apbdma 4>,
|
||||
<&apbdma 6>, <&apbdma 6>,
|
||||
<&apbdma 7>, <&apbdma 7>,
|
||||
<&apbdma 12>, <&apbdma 12>,
|
||||
<&apbdma 13>, <&apbdma 13>,
|
||||
<&apbdma 14>, <&apbdma 14>,
|
||||
<&apbdma 29>, <&apbdma 29>;
|
||||
dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
|
||||
"rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
|
||||
"rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
|
||||
"rx9", "tx9";
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
tegra_i2s0: i2s@70301000 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x70301000 0x100>;
|
||||
nvidia,ahub-cif-ids = <4 4>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S0>;
|
||||
resets = <&tegra_car 30>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_i2s1: i2s@70301100 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x70301100 0x100>;
|
||||
nvidia,ahub-cif-ids = <5 5>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S1>;
|
||||
resets = <&tegra_car 11>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_i2s2: i2s@70301200 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x70301200 0x100>;
|
||||
nvidia,ahub-cif-ids = <6 6>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S2>;
|
||||
resets = <&tegra_car 18>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_i2s3: i2s@70301300 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x70301300 0x100>;
|
||||
nvidia,ahub-cif-ids = <7 7>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S3>;
|
||||
resets = <&tegra_car 101>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tegra_i2s4: i2s@70301400 {
|
||||
compatible = "nvidia,tegra124-i2s";
|
||||
reg = <0x70301400 0x100>;
|
||||
nvidia,ahub-cif-ids = <8 8>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_I2S4>;
|
||||
resets = <&tegra_car 102>;
|
||||
reset-names = "i2s";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
|
@ -8,8 +8,8 @@ memory {
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
pll-supply = <&hdmi_pll_reg>;
|
||||
|
||||
|
@ -19,7 +19,7 @@ hdmi {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000014 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -27,20 +27,20 @@ state_default: pinmux {
|
|||
audio_refclk {
|
||||
nvidia,pins = "cdev1";
|
||||
nvidia,function = "plla_out";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
crt {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,function = "crt";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
dap3 {
|
||||
nvidia,pins = "dap3";
|
||||
nvidia,function = "dap3";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
displaya {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3",
|
||||
|
@ -50,155 +50,163 @@ displaya {
|
|||
"lhs", "lpw0", "lpw2", "lsc0",
|
||||
"lsc1", "lsck", "lsda", "lspi", "lvs";
|
||||
nvidia,function = "displaya";
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
gpio_dte {
|
||||
nvidia,pins = "dte";
|
||||
nvidia,function = "rsvd1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gpio_gmi {
|
||||
nvidia,pins = "ata", "atc", "atd", "ate",
|
||||
"dap1", "dap2", "dap4", "gpu", "irrx",
|
||||
"irtx", "spia", "spib", "spic";
|
||||
nvidia,function = "gmi";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gpio_pta {
|
||||
nvidia,pins = "pta";
|
||||
nvidia,function = "rsvd4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
gpio_uac {
|
||||
nvidia,pins = "uac";
|
||||
nvidia,function = "rsvd2";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
hdint {
|
||||
nvidia,pins = "hdint";
|
||||
nvidia,function = "hdmi";
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
i2c1 {
|
||||
nvidia,pins = "rm";
|
||||
nvidia,function = "i2c1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
i2c3 {
|
||||
nvidia,pins = "dtf";
|
||||
nvidia,function = "i2c3";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
i2cddc {
|
||||
nvidia,pins = "ddc";
|
||||
nvidia,function = "i2c2";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
i2cp {
|
||||
nvidia,pins = "i2cp";
|
||||
nvidia,function = "i2cp";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
irda {
|
||||
nvidia,pins = "uad";
|
||||
nvidia,function = "irda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
nand {
|
||||
nvidia,pins = "kbca", "kbcc", "kbcd",
|
||||
"kbce", "kbcf";
|
||||
nvidia,function = "nand";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
owc {
|
||||
nvidia,pins = "owc";
|
||||
nvidia,function = "owr";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
pmc {
|
||||
nvidia,pins = "pmc";
|
||||
nvidia,function = "pwr_on";
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pwm {
|
||||
nvidia,pins = "sdb", "sdc", "sdd";
|
||||
nvidia,function = "pwm";
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
sdio4 {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi1 {
|
||||
nvidia,pins = "spid", "spie", "spif";
|
||||
nvidia,function = "spi1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
spi4 {
|
||||
nvidia,pins = "slxa", "slxc", "slxd", "slxk";
|
||||
nvidia,function = "spi4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
uarta {
|
||||
nvidia,pins = "sdio1";
|
||||
nvidia,function = "uarta";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
uartd {
|
||||
nvidia,pins = "gmc";
|
||||
nvidia,function = "uartd";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
ulpi {
|
||||
nvidia,pins = "uaa", "uab", "uda";
|
||||
nvidia,function = "ulpi";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
ulpi_refclk {
|
||||
nvidia,pins = "cdev2";
|
||||
nvidia,function = "pllp_out4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
usb_gpio {
|
||||
nvidia,pins = "spig", "spih";
|
||||
nvidia,function = "spi2_alt";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
vi {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd";
|
||||
nvidia,function = "vi";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
vi_sc {
|
||||
nvidia,pins = "csus";
|
||||
nvidia,function = "vi_sensor_clk";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ac97: ac97@70002000 {
|
||||
status = "okay";
|
||||
nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
i2c@7000c000 {
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
@ -225,15 +233,15 @@ pmic: tps6586x@34 {
|
|||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
|
||||
sys-supply = <&vdd_5v0_reg>;
|
||||
sys-supply = <&vdd_3v3_reg>;
|
||||
vin-sm0-supply = <&sys_reg>;
|
||||
vin-sm1-supply = <&sys_reg>;
|
||||
vin-sm2-supply = <&sys_reg>;
|
||||
vinldo01-supply = <&sm2_reg>;
|
||||
vinldo23-supply = <&sm2_reg>;
|
||||
vinldo4-supply = <&sm2_reg>;
|
||||
vinldo678-supply = <&sm2_reg>;
|
||||
vinldo9-supply = <&sm2_reg>;
|
||||
vinldo23-supply = <&vdd_3v3_reg>;
|
||||
vinldo4-supply = <&vdd_3v3_reg>;
|
||||
vinldo678-supply = <&vdd_3v3_reg>;
|
||||
vinldo9-supply = <&vdd_3v3_reg>;
|
||||
|
||||
regulators {
|
||||
#address-cells = <1>;
|
||||
|
@ -250,8 +258,8 @@ regulator@1 {
|
|||
reg = <1>;
|
||||
regulator-compatible = "sm0";
|
||||
regulator-name = "vdd_sm0,vdd_core";
|
||||
regulator-min-microvolt = <1275000>;
|
||||
regulator-max-microvolt = <1275000>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
@ -259,8 +267,8 @@ regulator@2 {
|
|||
reg = <2>;
|
||||
regulator-compatible = "sm1";
|
||||
regulator-name = "vdd_sm1,vdd_cpu";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
@ -316,8 +324,8 @@ regulator@10 {
|
|||
reg = <10>;
|
||||
regulator-compatible = "ldo6";
|
||||
regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
};
|
||||
|
||||
hdmi_vdd_reg: regulator@11 {
|
||||
|
@ -362,7 +370,7 @@ temperature-sensor@4c {
|
|||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
pmc@7000e400 {
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <5000>;
|
||||
nvidia,cpu-pwr-off-time = <5000>;
|
||||
|
@ -442,14 +450,6 @@ emc-table@333000 {
|
|||
};
|
||||
};
|
||||
|
||||
ac97: ac97 {
|
||||
status = "okay";
|
||||
nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
|
||||
GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb@c5004000 {
|
||||
status = "okay";
|
||||
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
|
||||
|
@ -471,7 +471,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
@ -479,6 +479,33 @@ clk32k_in: clock {
|
|||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd_3v3_reg: regulator@100 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <100>;
|
||||
regulator-name = "vdd_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@101 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <101>;
|
||||
regulator-name = "internal_usb";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
|
||||
"nvidia,tegra-audio-wm9712";
|
||||
|
@ -498,31 +525,4 @@ sound {
|
|||
<&tegra_car TEGRA20_CLK_CDEV1>;
|
||||
clock-names = "pll_a", "pll_a_out0", "mclk";
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
vdd_5v0_reg: regulator@100 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <100>;
|
||||
regulator-name = "vdd_5v0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
regulator@101 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <101>;
|
||||
regulator-name = "internal_usb";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -10,8 +11,8 @@ memory {
|
|||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
|
@ -23,7 +24,7 @@ hdmi {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000014 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -184,50 +185,50 @@ conf_ata {
|
|||
"gmb", "gmc", "gmd", "gme", "gpu7",
|
||||
"gpv", "i2cp", "pta", "rm", "slxa",
|
||||
"slxk", "spia", "spib", "uac";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
conf_csus {
|
||||
nvidia,pins = "csus", "spid", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "dap2", "dap3", "dap4",
|
||||
"dtc", "dte", "dtf", "gpu", "sdio1",
|
||||
"slxc", "slxd", "spdi", "spdo", "spig",
|
||||
"uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "dta", "dtd", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"sdc";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "owc", "sdb";
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_irrx {
|
||||
nvidia,pins = "irrx", "irtx", "sdd", "spic",
|
||||
"spie", "spih", "uaa", "uab", "uad",
|
||||
"uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
|
@ -237,12 +238,12 @@ conf_ld0 {
|
|||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "pmc";
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -415,7 +416,124 @@ temperature-sensor@4c {
|
|||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
kbc@7000e200 {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <2>;
|
||||
nvidia,repeat-delay-ms = <160>;
|
||||
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||||
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
|
||||
linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
|
||||
MATRIX_KEY(0x00, 0x03, KEY_S)
|
||||
MATRIX_KEY(0x00, 0x04, KEY_A)
|
||||
MATRIX_KEY(0x00, 0x05, KEY_Z)
|
||||
MATRIX_KEY(0x00, 0x07, KEY_FN)
|
||||
MATRIX_KEY(0x01, 0x07, KEY_MENU)
|
||||
MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
|
||||
MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
|
||||
MATRIX_KEY(0x03, 0x00, KEY_5)
|
||||
MATRIX_KEY(0x03, 0x01, KEY_4)
|
||||
MATRIX_KEY(0x03, 0x02, KEY_R)
|
||||
MATRIX_KEY(0x03, 0x03, KEY_E)
|
||||
MATRIX_KEY(0x03, 0x04, KEY_F)
|
||||
MATRIX_KEY(0x03, 0x05, KEY_D)
|
||||
MATRIX_KEY(0x03, 0x06, KEY_X)
|
||||
MATRIX_KEY(0x04, 0x00, KEY_7)
|
||||
MATRIX_KEY(0x04, 0x01, KEY_6)
|
||||
MATRIX_KEY(0x04, 0x02, KEY_T)
|
||||
MATRIX_KEY(0x04, 0x03, KEY_H)
|
||||
MATRIX_KEY(0x04, 0x04, KEY_G)
|
||||
MATRIX_KEY(0x04, 0x05, KEY_V)
|
||||
MATRIX_KEY(0x04, 0x06, KEY_C)
|
||||
MATRIX_KEY(0x04, 0x07, KEY_SPACE)
|
||||
MATRIX_KEY(0x05, 0x00, KEY_9)
|
||||
MATRIX_KEY(0x05, 0x01, KEY_8)
|
||||
MATRIX_KEY(0x05, 0x02, KEY_U)
|
||||
MATRIX_KEY(0x05, 0x03, KEY_Y)
|
||||
MATRIX_KEY(0x05, 0x04, KEY_J)
|
||||
MATRIX_KEY(0x05, 0x05, KEY_N)
|
||||
MATRIX_KEY(0x05, 0x06, KEY_B)
|
||||
MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
|
||||
MATRIX_KEY(0x06, 0x00, KEY_MINUS)
|
||||
MATRIX_KEY(0x06, 0x01, KEY_0)
|
||||
MATRIX_KEY(0x06, 0x02, KEY_O)
|
||||
MATRIX_KEY(0x06, 0x03, KEY_I)
|
||||
MATRIX_KEY(0x06, 0x04, KEY_L)
|
||||
MATRIX_KEY(0x06, 0x05, KEY_K)
|
||||
MATRIX_KEY(0x06, 0x06, KEY_COMMA)
|
||||
MATRIX_KEY(0x06, 0x07, KEY_M)
|
||||
MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
|
||||
MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
|
||||
MATRIX_KEY(0x07, 0x03, KEY_ENTER)
|
||||
MATRIX_KEY(0x07, 0x07, KEY_MENU)
|
||||
MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
|
||||
MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
|
||||
MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
|
||||
MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
|
||||
MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
|
||||
MATRIX_KEY(0x0B, 0x01, KEY_P)
|
||||
MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
|
||||
MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
|
||||
MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
|
||||
MATRIX_KEY(0x0B, 0x05, KEY_DOT)
|
||||
MATRIX_KEY(0x0C, 0x00, KEY_F10)
|
||||
MATRIX_KEY(0x0C, 0x01, KEY_F9)
|
||||
MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
|
||||
MATRIX_KEY(0x0C, 0x03, KEY_3)
|
||||
MATRIX_KEY(0x0C, 0x04, KEY_2)
|
||||
MATRIX_KEY(0x0C, 0x05, KEY_UP)
|
||||
MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
|
||||
MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
|
||||
MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
|
||||
MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
|
||||
MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
|
||||
MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
|
||||
MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
|
||||
MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
|
||||
MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
|
||||
MATRIX_KEY(0x0E, 0x00, KEY_F11)
|
||||
MATRIX_KEY(0x0E, 0x01, KEY_F12)
|
||||
MATRIX_KEY(0x0E, 0x02, KEY_F8)
|
||||
MATRIX_KEY(0x0E, 0x03, KEY_Q)
|
||||
MATRIX_KEY(0x0E, 0x04, KEY_F4)
|
||||
MATRIX_KEY(0x0E, 0x05, KEY_F3)
|
||||
MATRIX_KEY(0x0E, 0x06, KEY_1)
|
||||
MATRIX_KEY(0x0E, 0x07, KEY_F7)
|
||||
MATRIX_KEY(0x0F, 0x00, KEY_ESC)
|
||||
MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
|
||||
MATRIX_KEY(0x0F, 0x02, KEY_F5)
|
||||
MATRIX_KEY(0x0F, 0x03, KEY_TAB)
|
||||
MATRIX_KEY(0x0F, 0x04, KEY_F1)
|
||||
MATRIX_KEY(0x0F, 0x05, KEY_F2)
|
||||
MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
|
||||
MATRIX_KEY(0x0F, 0x07, KEY_F6)
|
||||
MATRIX_KEY(0x14, 0x00, KEY_KP7)
|
||||
MATRIX_KEY(0x15, 0x00, KEY_KP9)
|
||||
MATRIX_KEY(0x15, 0x01, KEY_KP8)
|
||||
MATRIX_KEY(0x15, 0x02, KEY_KP4)
|
||||
MATRIX_KEY(0x15, 0x04, KEY_KP1)
|
||||
MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
|
||||
MATRIX_KEY(0x16, 0x02, KEY_KP6)
|
||||
MATRIX_KEY(0x16, 0x03, KEY_KP5)
|
||||
MATRIX_KEY(0x16, 0x04, KEY_KP3)
|
||||
MATRIX_KEY(0x16, 0x05, KEY_KP2)
|
||||
MATRIX_KEY(0x16, 0x07, KEY_KP0)
|
||||
MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
|
||||
MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
|
||||
MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
|
||||
MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
|
||||
MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
|
||||
MATRIX_KEY(0x1D, 0x03, KEY_HOME)
|
||||
MATRIX_KEY(0x1D, 0x04, KEY_END)
|
||||
MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
|
||||
MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
|
||||
MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
|
||||
MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
|
||||
MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
|
||||
MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
|
||||
MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
|
||||
};
|
||||
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <5000>;
|
||||
|
@ -425,7 +543,7 @@ pmc {
|
|||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie-controller@80003000 {
|
||||
pex-clk-supply = <&pci_clk_reg>;
|
||||
vdd-supply = <&pci_vdd_reg>;
|
||||
status = "okay";
|
||||
|
@ -488,7 +606,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
@ -502,128 +620,11 @@ gpio-keys {
|
|||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <2>;
|
||||
nvidia,repeat-delay-ms = <160>;
|
||||
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||||
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
|
||||
linux,keymap = <0x00020011 /* KEY_W */
|
||||
0x0003001F /* KEY_S */
|
||||
0x0004001E /* KEY_A */
|
||||
0x0005002C /* KEY_Z */
|
||||
0x000701D0 /* KEY_FN */
|
||||
0x0107008B /* KEY_MENU */
|
||||
0x02060038 /* KEY_LEFTALT */
|
||||
0x02070064 /* KEY_RIGHTALT */
|
||||
0x03000006 /* KEY_5 */
|
||||
0x03010005 /* KEY_4 */
|
||||
0x03020013 /* KEY_R */
|
||||
0x03030012 /* KEY_E */
|
||||
0x03040021 /* KEY_F */
|
||||
0x03050020 /* KEY_D */
|
||||
0x0306002D /* KEY_X */
|
||||
0x04000008 /* KEY_7 */
|
||||
0x04010007 /* KEY_6 */
|
||||
0x04020014 /* KEY_T */
|
||||
0x04030023 /* KEY_H */
|
||||
0x04040022 /* KEY_G */
|
||||
0x0405002F /* KEY_V */
|
||||
0x0406002E /* KEY_C */
|
||||
0x04070039 /* KEY_SPACE */
|
||||
0x0500000A /* KEY_9 */
|
||||
0x05010009 /* KEY_8 */
|
||||
0x05020016 /* KEY_U */
|
||||
0x05030015 /* KEY_Y */
|
||||
0x05040024 /* KEY_J */
|
||||
0x05050031 /* KEY_N */
|
||||
0x05060030 /* KEY_B */
|
||||
0x0507002B /* KEY_BACKSLASH */
|
||||
0x0600000C /* KEY_MINUS */
|
||||
0x0601000B /* KEY_0 */
|
||||
0x06020018 /* KEY_O */
|
||||
0x06030017 /* KEY_I */
|
||||
0x06040026 /* KEY_L */
|
||||
0x06050025 /* KEY_K */
|
||||
0x06060033 /* KEY_COMMA */
|
||||
0x06070032 /* KEY_M */
|
||||
0x0701000D /* KEY_EQUAL */
|
||||
0x0702001B /* KEY_RIGHTBRACE */
|
||||
0x0703001C /* KEY_ENTER */
|
||||
0x0707008B /* KEY_MENU */
|
||||
0x0804002A /* KEY_LEFTSHIFT */
|
||||
0x08050036 /* KEY_RIGHTSHIFT */
|
||||
0x0905001D /* KEY_LEFTCTRL */
|
||||
0x09070061 /* KEY_RIGHTCTRL */
|
||||
0x0B00001A /* KEY_LEFTBRACE */
|
||||
0x0B010019 /* KEY_P */
|
||||
0x0B020028 /* KEY_APOSTROPHE */
|
||||
0x0B030027 /* KEY_SEMICOLON */
|
||||
0x0B040035 /* KEY_SLASH */
|
||||
0x0B050034 /* KEY_DOT */
|
||||
0x0C000044 /* KEY_F10 */
|
||||
0x0C010043 /* KEY_F9 */
|
||||
0x0C02000E /* KEY_BACKSPACE */
|
||||
0x0C030004 /* KEY_3 */
|
||||
0x0C040003 /* KEY_2 */
|
||||
0x0C050067 /* KEY_UP */
|
||||
0x0C0600D2 /* KEY_PRINT */
|
||||
0x0C070077 /* KEY_PAUSE */
|
||||
0x0D00006E /* KEY_INSERT */
|
||||
0x0D01006F /* KEY_DELETE */
|
||||
0x0D030068 /* KEY_PAGEUP */
|
||||
0x0D04006D /* KEY_PAGEDOWN */
|
||||
0x0D05006A /* KEY_RIGHT */
|
||||
0x0D06006C /* KEY_DOWN */
|
||||
0x0D070069 /* KEY_LEFT */
|
||||
0x0E000057 /* KEY_F11 */
|
||||
0x0E010058 /* KEY_F12 */
|
||||
0x0E020042 /* KEY_F8 */
|
||||
0x0E030010 /* KEY_Q */
|
||||
0x0E04003E /* KEY_F4 */
|
||||
0x0E05003D /* KEY_F3 */
|
||||
0x0E060002 /* KEY_1 */
|
||||
0x0E070041 /* KEY_F7 */
|
||||
0x0F000001 /* KEY_ESC */
|
||||
0x0F010029 /* KEY_GRAVE */
|
||||
0x0F02003F /* KEY_F5 */
|
||||
0x0F03000F /* KEY_TAB */
|
||||
0x0F04003B /* KEY_F1 */
|
||||
0x0F05003C /* KEY_F2 */
|
||||
0x0F06003A /* KEY_CAPSLOCK */
|
||||
0x0F070040 /* KEY_F6 */
|
||||
0x14000047 /* KEY_KP7 */
|
||||
0x15000049 /* KEY_KP9 */
|
||||
0x15010048 /* KEY_KP8 */
|
||||
0x1502004B /* KEY_KP4 */
|
||||
0x1504004F /* KEY_KP1 */
|
||||
0x1601004E /* KEY_KPSLASH */
|
||||
0x1602004D /* KEY_KP6 */
|
||||
0x1603004C /* KEY_KP5 */
|
||||
0x16040051 /* KEY_KP3 */
|
||||
0x16050050 /* KEY_KP2 */
|
||||
0x16070052 /* KEY_KP0 */
|
||||
0x1B010037 /* KEY_KPASTERISK */
|
||||
0x1B03004A /* KEY_KPMINUS */
|
||||
0x1B04004E /* KEY_KPPLUS */
|
||||
0x1B050053 /* KEY_KPDOT */
|
||||
0x1C050073 /* KEY_VOLUMEUP */
|
||||
0x1D030066 /* KEY_HOME */
|
||||
0x1D04006B /* KEY_END */
|
||||
0x1D0500E1 /* KEY_BRIGHTNESSUP */
|
||||
0x1D060072 /* KEY_VOLUMEDOWN */
|
||||
0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
|
||||
0x1E000045 /* KEY_NUMLOCK */
|
||||
0x1E010046 /* KEY_SCROLLLOCK */
|
||||
0x1E020071 /* KEY_MUTE */
|
||||
0x1F0400D6>; /* KEY_QUESTION */
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -6,36 +6,48 @@ / {
|
|||
model = "Toradex Colibri T20 512MB on Iris";
|
||||
compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000014 {
|
||||
state_default: pinmux {
|
||||
hdint {
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
i2cddc {
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
sdio4 {
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
uarta {
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
uartd {
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c_ddc: i2c@7000c400 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@c5000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -52,18 +64,6 @@ usb-phy@c5008000 {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
serial@70006000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@70006300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c_ddc: i2c@7000c400 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
|
|
|
@ -6,7 +6,7 @@ / {
|
|||
model = "Avionic Design Medcom-Wide board";
|
||||
compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
pwm {
|
||||
pwm@7000a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -10,8 +11,8 @@ memory {
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
|
@ -23,7 +24,7 @@ hdmi {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000014 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -177,39 +178,39 @@ conf_ata {
|
|||
"gpu", "gpu7", "gpv", "i2cp", "pta",
|
||||
"rm", "sdio1", "slxk", "spdo", "uac",
|
||||
"uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "dap3", "dap4", "dtb",
|
||||
"dtc", "dte", "slxa", "slxc", "slxd",
|
||||
"spdi";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_csus {
|
||||
nvidia,pins = "csus", "spia", "spib", "spid",
|
||||
"spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "irrx", "irtx", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"spic", "spig", "uaa", "uab";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
|
||||
"spie", "spih", "uad", "uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "ld0", "ld1", "ld2",
|
||||
|
@ -218,23 +219,23 @@ conf_hdint {
|
|||
"ld13", "ld14", "ld15", "ld16", "ld17",
|
||||
"ldc", "ldi", "lhs", "lsc0", "lspi",
|
||||
"lvs", "pmc";
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
};
|
||||
conf_lcsn {
|
||||
nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
|
||||
"lm0", "lm1", "lpp", "lpw0", "lpw1",
|
||||
"lpw2", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "lvp1", "sdb";
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -268,7 +269,7 @@ hdmi_ddc: i2c@7000c400 {
|
|||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
nvec {
|
||||
nvec@7000c500 {
|
||||
compatible = "nvidia,nvec";
|
||||
reg = <0x7000c500 0x100>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -417,7 +418,7 @@ adt7461@4c {
|
|||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <2000>;
|
||||
|
@ -474,7 +475,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
@ -488,7 +489,7 @@ gpio-keys {
|
|||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -6,8 +6,8 @@ / {
|
|||
model = "Avionic Design Plutux board";
|
||||
compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -10,8 +11,8 @@ memory {
|
|||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
|
@ -23,7 +24,7 @@ hdmi {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000014 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -189,53 +190,53 @@ conf_ata {
|
|||
"irtx", "pta", "rm", "sdc", "sdd",
|
||||
"slxd", "slxk", "spdi", "spdo", "uac",
|
||||
"uad", "uca", "ucb", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ate {
|
||||
nvidia,pins = "ate", "csus", "dap3",
|
||||
"gpv", "owc", "slxc", "spib", "spid",
|
||||
"spie";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "gmb", "slxa", "spia",
|
||||
"spig", "spih";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_dte {
|
||||
nvidia,pins = "dte", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0";
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf", "sdio1", "spic", "uaa",
|
||||
"uab";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
|
@ -245,22 +246,22 @@ conf_ld0 {
|
|||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "pmc", "sdb";
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
};
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <0>;
|
||||
nvidia,low-power-mode = <3>;
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <3>;
|
||||
nvidia,slew-rate-falling = <3>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -386,6 +387,13 @@ i2c@7000d000 {
|
|||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
magnetometer@c {
|
||||
compatible = "ak,ak8975";
|
||||
reg = <0xc>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pmic: tps6586x@34 {
|
||||
compatible = "ti,tps6586x";
|
||||
reg = <0x34>;
|
||||
|
@ -507,16 +515,149 @@ temperature-sensor@4c {
|
|||
compatible = "onnn,nct1008";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
magnetometer@c {
|
||||
compatible = "ak,ak8975";
|
||||
reg = <0xc>;
|
||||
interrupt-parent = <&gpio>;
|
||||
interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
kbc@7000e200 {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <32>;
|
||||
nvidia,repeat-delay-ms = <160>;
|
||||
nvidia,ghost-filter;
|
||||
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||||
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
|
||||
linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
|
||||
MATRIX_KEY(0x00, 0x03, KEY_S)
|
||||
MATRIX_KEY(0x00, 0x04, KEY_A)
|
||||
MATRIX_KEY(0x00, 0x05, KEY_Z)
|
||||
MATRIX_KEY(0x00, 0x07, KEY_FN)
|
||||
|
||||
MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA)
|
||||
MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT)
|
||||
MATRIX_KEY(0x02, 0x07, KEY_LEFTALT)
|
||||
|
||||
MATRIX_KEY(0x03, 0x00, KEY_5)
|
||||
MATRIX_KEY(0x03, 0x01, KEY_4)
|
||||
MATRIX_KEY(0x03, 0x02, KEY_R)
|
||||
MATRIX_KEY(0x03, 0x03, KEY_E)
|
||||
MATRIX_KEY(0x03, 0x04, KEY_F)
|
||||
MATRIX_KEY(0x03, 0x05, KEY_D)
|
||||
MATRIX_KEY(0x03, 0x06, KEY_X)
|
||||
|
||||
MATRIX_KEY(0x04, 0x00, KEY_7)
|
||||
MATRIX_KEY(0x04, 0x01, KEY_6)
|
||||
MATRIX_KEY(0x04, 0x02, KEY_T)
|
||||
MATRIX_KEY(0x04, 0x03, KEY_H)
|
||||
MATRIX_KEY(0x04, 0x04, KEY_G)
|
||||
MATRIX_KEY(0x04, 0x05, KEY_V)
|
||||
MATRIX_KEY(0x04, 0x06, KEY_C)
|
||||
MATRIX_KEY(0x04, 0x07, KEY_SPACE)
|
||||
|
||||
MATRIX_KEY(0x05, 0x00, KEY_9)
|
||||
MATRIX_KEY(0x05, 0x01, KEY_8)
|
||||
MATRIX_KEY(0x05, 0x02, KEY_U)
|
||||
MATRIX_KEY(0x05, 0x03, KEY_Y)
|
||||
MATRIX_KEY(0x05, 0x04, KEY_J)
|
||||
MATRIX_KEY(0x05, 0x05, KEY_N)
|
||||
MATRIX_KEY(0x05, 0x06, KEY_B)
|
||||
MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
|
||||
|
||||
MATRIX_KEY(0x06, 0x00, KEY_MINUS)
|
||||
MATRIX_KEY(0x06, 0x01, KEY_0)
|
||||
MATRIX_KEY(0x06, 0x02, KEY_O)
|
||||
MATRIX_KEY(0x06, 0x03, KEY_I)
|
||||
MATRIX_KEY(0x06, 0x04, KEY_L)
|
||||
MATRIX_KEY(0x06, 0x05, KEY_K)
|
||||
MATRIX_KEY(0x06, 0x06, KEY_COMMA)
|
||||
MATRIX_KEY(0x06, 0x07, KEY_M)
|
||||
|
||||
MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
|
||||
MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
|
||||
MATRIX_KEY(0x07, 0x03, KEY_ENTER)
|
||||
MATRIX_KEY(0x07, 0x07, KEY_MENU)
|
||||
|
||||
MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT)
|
||||
MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT)
|
||||
|
||||
MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL)
|
||||
MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL)
|
||||
|
||||
MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
|
||||
MATRIX_KEY(0x0B, 0x01, KEY_P)
|
||||
MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
|
||||
MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
|
||||
MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
|
||||
MATRIX_KEY(0x0B, 0x05, KEY_DOT)
|
||||
|
||||
MATRIX_KEY(0x0C, 0x00, KEY_F10)
|
||||
MATRIX_KEY(0x0C, 0x01, KEY_F9)
|
||||
MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
|
||||
MATRIX_KEY(0x0C, 0x03, KEY_3)
|
||||
MATRIX_KEY(0x0C, 0x04, KEY_2)
|
||||
MATRIX_KEY(0x0C, 0x05, KEY_UP)
|
||||
MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
|
||||
MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
|
||||
|
||||
MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
|
||||
MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
|
||||
MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
|
||||
MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
|
||||
MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
|
||||
MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
|
||||
MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
|
||||
|
||||
MATRIX_KEY(0x0E, 0x00, KEY_F11)
|
||||
MATRIX_KEY(0x0E, 0x01, KEY_F12)
|
||||
MATRIX_KEY(0x0E, 0x02, KEY_F8)
|
||||
MATRIX_KEY(0x0E, 0x03, KEY_Q)
|
||||
MATRIX_KEY(0x0E, 0x04, KEY_F4)
|
||||
MATRIX_KEY(0x0E, 0x05, KEY_F3)
|
||||
MATRIX_KEY(0x0E, 0x06, KEY_1)
|
||||
MATRIX_KEY(0x0E, 0x07, KEY_F7)
|
||||
|
||||
MATRIX_KEY(0x0F, 0x00, KEY_ESC)
|
||||
MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
|
||||
MATRIX_KEY(0x0F, 0x02, KEY_F5)
|
||||
MATRIX_KEY(0x0F, 0x03, KEY_TAB)
|
||||
MATRIX_KEY(0x0F, 0x04, KEY_F1)
|
||||
MATRIX_KEY(0x0F, 0x05, KEY_F2)
|
||||
MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
|
||||
MATRIX_KEY(0x0F, 0x07, KEY_F6)
|
||||
|
||||
/* Software Handled Function Keys */
|
||||
MATRIX_KEY(0x14, 0x00, KEY_KP7)
|
||||
|
||||
MATRIX_KEY(0x15, 0x00, KEY_KP9)
|
||||
MATRIX_KEY(0x15, 0x01, KEY_KP8)
|
||||
MATRIX_KEY(0x15, 0x02, KEY_KP4)
|
||||
MATRIX_KEY(0x15, 0x04, KEY_KP1)
|
||||
|
||||
MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
|
||||
MATRIX_KEY(0x16, 0x02, KEY_KP6)
|
||||
MATRIX_KEY(0x16, 0x03, KEY_KP5)
|
||||
MATRIX_KEY(0x16, 0x04, KEY_KP3)
|
||||
MATRIX_KEY(0x16, 0x05, KEY_KP2)
|
||||
MATRIX_KEY(0x16, 0x07, KEY_KP0)
|
||||
|
||||
MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
|
||||
MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
|
||||
MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
|
||||
MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
|
||||
|
||||
MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
|
||||
|
||||
MATRIX_KEY(0x1D, 0x03, KEY_HOME)
|
||||
MATRIX_KEY(0x1D, 0x04, KEY_END)
|
||||
MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN)
|
||||
MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
|
||||
MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP)
|
||||
|
||||
MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
|
||||
MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
|
||||
MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
|
||||
|
||||
MATRIX_KEY(0x1F, 0x04, KEY_HELP)>;
|
||||
};
|
||||
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <5000>;
|
||||
|
@ -621,7 +762,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
@ -635,7 +776,7 @@ gpio-keys {
|
|||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
|
@ -649,145 +790,6 @@ lid {
|
|||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <32>;
|
||||
nvidia,repeat-delay-ms = <160>;
|
||||
nvidia,ghost-filter;
|
||||
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
|
||||
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
|
||||
linux,keymap = <0x00020011 /* KEY_W */
|
||||
0x0003001F /* KEY_S */
|
||||
0x0004001E /* KEY_A */
|
||||
0x0005002C /* KEY_Z */
|
||||
0x000701d0 /* KEY_FN */
|
||||
|
||||
0x0107007D /* KEY_LEFTMETA */
|
||||
0x02060064 /* KEY_RIGHTALT */
|
||||
0x02070038 /* KEY_LEFTALT */
|
||||
|
||||
0x03000006 /* KEY_5 */
|
||||
0x03010005 /* KEY_4 */
|
||||
0x03020013 /* KEY_R */
|
||||
0x03030012 /* KEY_E */
|
||||
0x03040021 /* KEY_F */
|
||||
0x03050020 /* KEY_D */
|
||||
0x0306002D /* KEY_X */
|
||||
|
||||
0x04000008 /* KEY_7 */
|
||||
0x04010007 /* KEY_6 */
|
||||
0x04020014 /* KEY_T */
|
||||
0x04030023 /* KEY_H */
|
||||
0x04040022 /* KEY_G */
|
||||
0x0405002F /* KEY_V */
|
||||
0x0406002E /* KEY_C */
|
||||
0x04070039 /* KEY_SPACE */
|
||||
|
||||
0x0500000A /* KEY_9 */
|
||||
0x05010009 /* KEY_8 */
|
||||
0x05020016 /* KEY_U */
|
||||
0x05030015 /* KEY_Y */
|
||||
0x05040024 /* KEY_J */
|
||||
0x05050031 /* KEY_N */
|
||||
0x05060030 /* KEY_B */
|
||||
0x0507002B /* KEY_BACKSLASH */
|
||||
|
||||
0x0600000C /* KEY_MINUS */
|
||||
0x0601000B /* KEY_0 */
|
||||
0x06020018 /* KEY_O */
|
||||
0x06030017 /* KEY_I */
|
||||
0x06040026 /* KEY_L */
|
||||
0x06050025 /* KEY_K */
|
||||
0x06060033 /* KEY_COMMA */
|
||||
0x06070032 /* KEY_M */
|
||||
|
||||
0x0701000D /* KEY_EQUAL */
|
||||
0x0702001B /* KEY_RIGHTBRACE */
|
||||
0x0703001C /* KEY_ENTER */
|
||||
0x0707008B /* KEY_MENU */
|
||||
|
||||
0x08040036 /* KEY_RIGHTSHIFT */
|
||||
0x0805002A /* KEY_LEFTSHIFT */
|
||||
|
||||
0x09050061 /* KEY_RIGHTCTRL */
|
||||
0x0907001D /* KEY_LEFTCTRL */
|
||||
|
||||
0x0B00001A /* KEY_LEFTBRACE */
|
||||
0x0B010019 /* KEY_P */
|
||||
0x0B020028 /* KEY_APOSTROPHE */
|
||||
0x0B030027 /* KEY_SEMICOLON */
|
||||
0x0B040035 /* KEY_SLASH */
|
||||
0x0B050034 /* KEY_DOT */
|
||||
|
||||
0x0C000044 /* KEY_F10 */
|
||||
0x0C010043 /* KEY_F9 */
|
||||
0x0C02000E /* KEY_BACKSPACE */
|
||||
0x0C030004 /* KEY_3 */
|
||||
0x0C040003 /* KEY_2 */
|
||||
0x0C050067 /* KEY_UP */
|
||||
0x0C0600D2 /* KEY_PRINT */
|
||||
0x0C070077 /* KEY_PAUSE */
|
||||
|
||||
0x0D00006E /* KEY_INSERT */
|
||||
0x0D01006F /* KEY_DELETE */
|
||||
0x0D030068 /* KEY_PAGEUP */
|
||||
0x0D04006D /* KEY_PAGEDOWN */
|
||||
0x0D05006A /* KEY_RIGHT */
|
||||
0x0D06006C /* KEY_DOWN */
|
||||
0x0D070069 /* KEY_LEFT */
|
||||
|
||||
0x0E000057 /* KEY_F11 */
|
||||
0x0E010058 /* KEY_F12 */
|
||||
0x0E020042 /* KEY_F8 */
|
||||
0x0E030010 /* KEY_Q */
|
||||
0x0E04003E /* KEY_F4 */
|
||||
0x0E05003D /* KEY_F3 */
|
||||
0x0E060002 /* KEY_1 */
|
||||
0x0E070041 /* KEY_F7 */
|
||||
|
||||
0x0F000001 /* KEY_ESC */
|
||||
0x0F010029 /* KEY_GRAVE */
|
||||
0x0F02003F /* KEY_F5 */
|
||||
0x0F03000F /* KEY_TAB */
|
||||
0x0F04003B /* KEY_F1 */
|
||||
0x0F05003C /* KEY_F2 */
|
||||
0x0F06003A /* KEY_CAPSLOCK */
|
||||
0x0F070040 /* KEY_F6 */
|
||||
|
||||
/* Software Handled Function Keys */
|
||||
0x14000047 /* KEY_KP7 */
|
||||
|
||||
0x15000049 /* KEY_KP9 */
|
||||
0x15010048 /* KEY_KP8 */
|
||||
0x1502004B /* KEY_KP4 */
|
||||
0x1504004F /* KEY_KP1 */
|
||||
|
||||
0x1601004E /* KEY_KPSLASH */
|
||||
0x1602004D /* KEY_KP6 */
|
||||
0x1603004C /* KEY_KP5 */
|
||||
0x16040051 /* KEY_KP3 */
|
||||
0x16050050 /* KEY_KP2 */
|
||||
0x16070052 /* KEY_KP0 */
|
||||
|
||||
0x1B010037 /* KEY_KPASTERISK */
|
||||
0x1B03004A /* KEY_KPMINUS */
|
||||
0x1B04004E /* KEY_KPPLUS */
|
||||
0x1B050053 /* KEY_KPDOT */
|
||||
|
||||
0x1C050073 /* KEY_VOLUMEUP */
|
||||
|
||||
0x1D030066 /* KEY_HOME */
|
||||
0x1D04006B /* KEY_END */
|
||||
0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
|
||||
0x1D060072 /* KEY_VOLUMEDOWN */
|
||||
0x1D0700E1 /* KEY_BRIGHTNESSUP */
|
||||
|
||||
0x1E000045 /* KEY_NUMLOCK */
|
||||
0x1E010046 /* KEY_SCROLLLOCK */
|
||||
0x1E020071 /* KEY_MUTE */
|
||||
|
||||
0x1F04008A>; /* KEY_HELP */
|
||||
};
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -8,8 +8,8 @@ memory {
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
pll-supply = <&hdmi_pll_reg>;
|
||||
|
||||
|
@ -19,7 +19,7 @@ hdmi {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000014 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -176,50 +176,50 @@ conf_ata {
|
|||
"gmb", "gmc", "gmd", "gme", "gpu7",
|
||||
"gpv", "i2cp", "pta", "rm", "slxa",
|
||||
"slxk", "spia", "spib", "uac";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
conf_csus {
|
||||
nvidia,pins = "csus", "spid", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "dap2", "dap3", "dap4",
|
||||
"dtc", "dte", "dtf", "gpu", "sdio1",
|
||||
"slxc", "slxd", "spdi", "spdo", "spig",
|
||||
"uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "dta", "dtd", "kbca",
|
||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||
"sdc";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "owc", "sdb";
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_irrx {
|
||||
nvidia,pins = "irrx", "irtx", "sdd", "spic",
|
||||
"spie", "spih", "uaa", "uab", "uad",
|
||||
"uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
|
@ -229,12 +229,12 @@ conf_ld0 {
|
|||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "pmc";
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -457,7 +457,7 @@ temperature-sensor@4c {
|
|||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <5000>;
|
||||
|
@ -467,7 +467,7 @@ pmc {
|
|||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie-controller@80003000 {
|
||||
pex-clk-supply = <&pci_clk_reg>;
|
||||
vdd-supply = <&pci_vdd_reg>;
|
||||
};
|
||||
|
@ -492,7 +492,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
|
|
@ -6,8 +6,8 @@ / {
|
|||
model = "Avionic Design Tamonten Evaluation Carrier";
|
||||
compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
@ -32,7 +32,7 @@ wm8903: wm8903@1a {
|
|||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie-controller@80003000 {
|
||||
status = "okay";
|
||||
|
||||
pci@1,0 {
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -10,8 +11,8 @@ memory {
|
|||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
|
@ -23,7 +24,7 @@ hdmi {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000014 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -191,49 +192,49 @@ conf_ata {
|
|||
"dtb", "dtc", "dtd", "dte", "gmb",
|
||||
"gme", "i2cp", "pta", "slxc", "slxd",
|
||||
"spdi", "spdo", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_atb {
|
||||
nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
|
||||
"gma", "gmc", "gmd", "gpu", "gpu7",
|
||||
"gpv", "sdio1", "slxa", "slxk", "uac";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
conf_csus {
|
||||
nvidia,pins = "csus", "spia", "spib",
|
||||
"spid", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ddc {
|
||||
nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsc1", "lsck", "lsda", "lsdi",
|
||||
"lvp0", "pmc";
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_irrx {
|
||||
nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
|
||||
"kbcc", "kbcd", "kbce", "kbcf", "owc",
|
||||
"spic", "spie", "spig", "spih", "uaa",
|
||||
"uab", "uad", "uca", "ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
|
@ -243,17 +244,17 @@ conf_ld0 {
|
|||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
|
||||
"lvs", "sdb";
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
};
|
||||
conf_spif {
|
||||
nvidia,pins = "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -301,7 +302,7 @@ rtc@56 {
|
|||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
pmc@7000e400 {
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <5000>;
|
||||
nvidia,cpu-pwr-off-time = <5000>;
|
||||
|
@ -310,7 +311,7 @@ pmc {
|
|||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie-controller@80003000 {
|
||||
status = "okay";
|
||||
pex-clk-supply = <&pci_clk_reg>;
|
||||
vdd-supply = <&pci_vdd_reg>;
|
||||
|
@ -366,7 +367,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
@ -380,7 +381,7 @@ gpio-keys {
|
|||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -10,8 +11,8 @@ memory {
|
|||
reg = <0x00000000 0x40000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
|
@ -23,7 +24,7 @@ hdmi {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000014 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -189,50 +190,50 @@ conf_ata {
|
|||
"irtx", "pta", "rm", "sdc", "sdd",
|
||||
"slxc", "slxd", "slxk", "spdi", "spdo",
|
||||
"uac", "uad", "uca", "ucb", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ate {
|
||||
nvidia,pins = "ate", "csus", "dap3", "gmd",
|
||||
"gpv", "owc", "spia", "spib", "spic",
|
||||
"spid", "spie", "spig";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
|
||||
"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp", "gmb", "slxa", "spih";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_dte {
|
||||
nvidia,pins = "dte", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_hdint {
|
||||
nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
|
||||
"lpw1", "lsck", "lsda", "lsdi", "lvp0";
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_kbca {
|
||||
nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
|
||||
"kbce", "kbcf", "sdio1", "uaa", "uab";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_lc {
|
||||
nvidia,pins = "lc", "ls";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
};
|
||||
conf_ld0 {
|
||||
nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
|
||||
|
@ -242,22 +243,22 @@ conf_ld0 {
|
|||
"lhp1", "lhp2", "lhs", "lm0", "lpp",
|
||||
"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
|
||||
"lvp1", "lvs", "pmc", "sdb";
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
};
|
||||
drive_sdio1 {
|
||||
nvidia,pins = "drive_sdio1";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <1>;
|
||||
nvidia,low-power-mode = <3>;
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
|
||||
nvidia,pull-down-strength = <31>;
|
||||
nvidia,pull-up-strength = <31>;
|
||||
nvidia,slew-rate-rising = <3>;
|
||||
nvidia,slew-rate-falling = <3>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -492,7 +493,7 @@ temperature-sensor@4c {
|
|||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <2000>;
|
||||
|
@ -556,7 +557,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
@ -570,7 +571,7 @@ gpio-keys {
|
|||
power {
|
||||
label = "Power";
|
||||
gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
|
||||
linux,code = <116>; /* KEY_POWER */
|
||||
linux,code = <KEY_POWER>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "tegra20.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -10,8 +11,8 @@ memory {
|
|||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&hdmi_vdd_reg>;
|
||||
|
@ -23,7 +24,7 @@ hdmi {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000014 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -189,8 +190,8 @@ conf_ata {
|
|||
"kbcf", "sdc", "sdd", "spie", "spig",
|
||||
"spih", "uaa", "uab", "uad", "uca",
|
||||
"ucb";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_atd {
|
||||
nvidia,pins = "atd", "ate", "cdev1", "csus",
|
||||
|
@ -198,54 +199,54 @@ conf_atd {
|
|||
"dtf", "gpu", "gpu7", "gpv", "i2cp",
|
||||
"rm", "sdio1", "slxa", "slxc", "slxd",
|
||||
"slxk", "spdi", "spdo", "uac", "uda";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_cdev2 {
|
||||
nvidia,pins = "cdev2", "spia", "spib";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ck32 {
|
||||
nvidia,pins = "ck32", "ddrc", "lc", "pmca",
|
||||
"pmcb", "pmcc", "pmcd", "xm2c",
|
||||
"xm2d";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
conf_crtp {
|
||||
nvidia,pins = "crtp";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_dta {
|
||||
nvidia,pins = "dta", "dtb", "dtc", "dtd",
|
||||
"spid", "spif";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
conf_gme {
|
||||
nvidia,pins = "gme", "owc", "pta", "spic";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
conf_ld17_0 {
|
||||
nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
|
||||
"ld23_22";
|
||||
nvidia,pull = <1>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
||||
};
|
||||
conf_ls {
|
||||
nvidia,pins = "ls", "pmce";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
};
|
||||
drive_dap1 {
|
||||
nvidia,pins = "drive_dap1";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <1>;
|
||||
nvidia,low-power-mode = <0>;
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_8>;
|
||||
nvidia,pull-down-strength = <0>;
|
||||
nvidia,pull-up-strength = <0>;
|
||||
nvidia,slew-rate-rising = <0>;
|
||||
nvidia,slew-rate-falling = <0>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -495,7 +496,20 @@ vrtc {
|
|||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
kbc@7000e200 {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <20>;
|
||||
nvidia,repeat-delay-ms = <160>;
|
||||
nvidia,kbc-row-pins = <0 1 2>;
|
||||
nvidia,kbc-col-pins = <16 17>;
|
||||
nvidia,wakeup-source;
|
||||
linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER)
|
||||
MATRIX_KEY(0x01, 0x00, KEY_HOME)
|
||||
MATRIX_KEY(0x01, 0x01, KEY_BACK)
|
||||
MATRIX_KEY(0x02, 0x01, KEY_MENU)>;
|
||||
};
|
||||
|
||||
pmc@7000e400 {
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
nvidia,cpu-pwr-good-time = <2000>;
|
||||
|
@ -543,7 +557,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
@ -551,25 +565,12 @@ clk32k_in: clock {
|
|||
};
|
||||
};
|
||||
|
||||
kbc {
|
||||
status = "okay";
|
||||
nvidia,debounce-delay-ms = <20>;
|
||||
nvidia,repeat-delay-ms = <160>;
|
||||
nvidia,kbc-row-pins = <0 1 2>;
|
||||
nvidia,kbc-col-pins = <16 17>;
|
||||
nvidia,wakeup-source;
|
||||
linux,keymap = <0x00000074 /* KEY_POWER */
|
||||
0x01000066 /* KEY_HOME */
|
||||
0x0101009E /* KEY_BACK */
|
||||
0x0201008B>; /* KEY_MENU */
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb0_vbus_reg: regulator {
|
||||
usb0_vbus_reg: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "usb0_vbus";
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
#include <dt-bindings/clock/tegra20-car.h>
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
@ -16,7 +17,7 @@ aliases {
|
|||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
host1x {
|
||||
host1x@50000000 {
|
||||
compatible = "nvidia,tegra20-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00024000>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
|
||||
|
@ -30,7 +31,7 @@ host1x {
|
|||
|
||||
ranges = <0x54000000 0x54000000 0x04000000>;
|
||||
|
||||
mpe {
|
||||
mpe@54040000 {
|
||||
compatible = "nvidia,tegra20-mpe";
|
||||
reg = <0x54040000 0x00040000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -39,7 +40,7 @@ mpe {
|
|||
reset-names = "mpe";
|
||||
};
|
||||
|
||||
vi {
|
||||
vi@54080000 {
|
||||
compatible = "nvidia,tegra20-vi";
|
||||
reg = <0x54080000 0x00040000>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -48,7 +49,7 @@ vi {
|
|||
reset-names = "vi";
|
||||
};
|
||||
|
||||
epp {
|
||||
epp@540c0000 {
|
||||
compatible = "nvidia,tegra20-epp";
|
||||
reg = <0x540c0000 0x00040000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -57,7 +58,7 @@ epp {
|
|||
reset-names = "epp";
|
||||
};
|
||||
|
||||
isp {
|
||||
isp@54100000 {
|
||||
compatible = "nvidia,tegra20-isp";
|
||||
reg = <0x54100000 0x00040000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -66,7 +67,7 @@ isp {
|
|||
reset-names = "isp";
|
||||
};
|
||||
|
||||
gr2d {
|
||||
gr2d@54140000 {
|
||||
compatible = "nvidia,tegra20-gr2d";
|
||||
reg = <0x54140000 0x00040000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -75,9 +76,9 @@ gr2d {
|
|||
reset-names = "2d";
|
||||
};
|
||||
|
||||
gr3d {
|
||||
gr3d@54140000 {
|
||||
compatible = "nvidia,tegra20-gr3d";
|
||||
reg = <0x54180000 0x00040000>;
|
||||
reg = <0x54140000 0x00040000>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
|
||||
resets = <&tegra_car 24>;
|
||||
reset-names = "3d";
|
||||
|
@ -113,7 +114,7 @@ rgb {
|
|||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
hdmi@54280000 {
|
||||
compatible = "nvidia,tegra20-hdmi";
|
||||
reg = <0x54280000 0x00040000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -125,7 +126,7 @@ hdmi {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
tvo {
|
||||
tvo@542c0000 {
|
||||
compatible = "nvidia,tegra20-tvo";
|
||||
reg = <0x542c0000 0x00040000>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -133,9 +134,9 @@ tvo {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi {
|
||||
dsi@542c0000 {
|
||||
compatible = "nvidia,tegra20-dsi";
|
||||
reg = <0x54300000 0x00040000>;
|
||||
reg = <0x542c0000 0x00040000>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_DSI>;
|
||||
resets = <&tegra_car 48>;
|
||||
reset-names = "dsi";
|
||||
|
@ -151,7 +152,7 @@ timer@50004600 {
|
|||
clocks = <&tegra_car TEGRA20_CLK_TWD>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller {
|
||||
intc: interrupt-controller@50041000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x50041000 0x1000
|
||||
0x50040100 0x0100>;
|
||||
|
@ -159,7 +160,7 @@ intc: interrupt-controller {
|
|||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
cache-controller {
|
||||
cache-controller@50043000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <5 5 2>;
|
||||
|
@ -178,14 +179,14 @@ timer@60005000 {
|
|||
clocks = <&tegra_car TEGRA20_CLK_TIMER>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
tegra_car: clock@60006000 {
|
||||
compatible = "nvidia,tegra20-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
apbdma: dma {
|
||||
apbdma: dma@6000a000 {
|
||||
compatible = "nvidia,tegra20-apbdma";
|
||||
reg = <0x6000a000 0x1200>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -210,12 +211,12 @@ apbdma: dma {
|
|||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
ahb@6000c004 {
|
||||
compatible = "nvidia,tegra20-ahb";
|
||||
reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
|
||||
};
|
||||
|
||||
gpio: gpio {
|
||||
gpio: gpio@6000d000 {
|
||||
compatible = "nvidia,tegra20-gpio";
|
||||
reg = <0x6000d000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -231,7 +232,7 @@ gpio: gpio {
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
pinmux: pinmux {
|
||||
pinmux: pinmux@70000014 {
|
||||
compatible = "nvidia,tegra20-pinmux";
|
||||
reg = <0x70000014 0x10 /* Tri-state registers */
|
||||
0x70000080 0x20 /* Mux registers */
|
||||
|
@ -239,12 +240,12 @@ pinmux: pinmux {
|
|||
0x70000868 0xa8>; /* Pad control registers */
|
||||
};
|
||||
|
||||
das {
|
||||
das@70000c00 {
|
||||
compatible = "nvidia,tegra20-das";
|
||||
reg = <0x70000c00 0x80>;
|
||||
};
|
||||
|
||||
tegra_ac97: ac97 {
|
||||
tegra_ac97: ac97@70002000 {
|
||||
compatible = "nvidia,tegra20-ac97";
|
||||
reg = <0x70002000 0x200>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -352,7 +353,7 @@ uarte: serial@70006400 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm {
|
||||
pwm: pwm@7000a000 {
|
||||
compatible = "nvidia,tegra20-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
|
@ -362,7 +363,7 @@ pwm: pwm {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc {
|
||||
rtc@7000e000 {
|
||||
compatible = "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -503,7 +504,7 @@ spi@7000da00 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
kbc {
|
||||
kbc@7000e200 {
|
||||
compatible = "nvidia,tegra20-kbc";
|
||||
reg = <0x7000e200 0x100>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -513,7 +514,7 @@ kbc {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pmc {
|
||||
pmc@7000e400 {
|
||||
compatible = "nvidia,tegra20-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
|
||||
|
@ -527,7 +528,7 @@ memory-controller@7000f000 {
|
|||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
iommu {
|
||||
iommu@7000f024 {
|
||||
compatible = "nvidia,tegra20-gart";
|
||||
reg = <0x7000f024 0x00000018 /* controller registers */
|
||||
0x58000000 0x02000000>; /* GART aperture */
|
||||
|
@ -540,7 +541,7 @@ memory-controller@7000f400 {
|
|||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie-controller@80003000 {
|
||||
compatible = "nvidia,tegra20-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0x80003000 0x00000800 /* PADS registers */
|
||||
|
|
|
@ -10,7 +10,7 @@ memory {
|
|||
reg = <0x80000000 0x7ff00000>;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie-controller@00003000 {
|
||||
status = "okay";
|
||||
pex-clk-supply = <&sys_3v3_pexs_reg>;
|
||||
vdd-supply = <&ldo1_reg>;
|
||||
|
@ -31,8 +31,8 @@ pci@3,0 {
|
|||
};
|
||||
};
|
||||
|
||||
host1x {
|
||||
hdmi {
|
||||
host1x@50000000 {
|
||||
hdmi@54280000 {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&sys_3v3_reg>;
|
||||
|
@ -44,7 +44,7 @@ hdmi {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000868 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -52,8 +52,8 @@ state_default: pinmux {
|
|||
sdmmc1_clk_pz0 {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc1_cmd_pz1 {
|
||||
nvidia,pins = "sdmmc1_cmd_pz1",
|
||||
|
@ -62,14 +62,14 @@ sdmmc1_cmd_pz1 {
|
|||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat3_py4";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc3_clk_pa6 {
|
||||
nvidia,pins = "sdmmc3_clk_pa6";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc3_cmd_pa7 {
|
||||
nvidia,pins = "sdmmc3_cmd_pa7",
|
||||
|
@ -78,15 +78,15 @@ sdmmc3_cmd_pa7 {
|
|||
"sdmmc3_dat2_pb5",
|
||||
"sdmmc3_dat3_pb4";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
|
@ -98,8 +98,8 @@ sdmmc4_dat0_paa0 {
|
|||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
dap2_fs_pa2 {
|
||||
nvidia,pins = "dap2_fs_pa2",
|
||||
|
@ -107,18 +107,18 @@ dap2_fs_pa2 {
|
|||
"dap2_din_pa4",
|
||||
"dap2_dout_pa5";
|
||||
nvidia,function = "i2s1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
pex_l1_prsnt_n_pdd4 {
|
||||
nvidia,pins = "pex_l1_prsnt_n_pdd4",
|
||||
"pex_l1_clkreq_n_pdd6";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
};
|
||||
sdio3 {
|
||||
nvidia,pins = "drive_sdio3";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <0>;
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull-down-strength = <46>;
|
||||
nvidia,pull-up-strength = <42>;
|
||||
nvidia,slew-rate-rising = <1>;
|
||||
|
@ -159,7 +159,7 @@ i2c@7000d000 {
|
|||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
rt5640: rt5640 {
|
||||
rt5640: rt5640@1c {
|
||||
compatible = "realtek,rt5640";
|
||||
reg = <0x1c>;
|
||||
interrupt-parent = <&gpio>;
|
||||
|
@ -168,19 +168,6 @@ rt5640: rt5640 {
|
|||
<&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
tps62361 {
|
||||
compatible = "ti,tps62361";
|
||||
reg = <0x60>;
|
||||
|
||||
regulator-name = "tps62361-vout";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
ti,vsel0-state-high;
|
||||
ti,vsel1-state-high;
|
||||
};
|
||||
|
||||
pmic: tps65911@2d {
|
||||
compatible = "ti,tps65911";
|
||||
reg = <0x2d>;
|
||||
|
@ -284,6 +271,19 @@ ldo8_reg: ldo8 {
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps62361@60 {
|
||||
compatible = "ti,tps62361";
|
||||
reg = <0x60>;
|
||||
|
||||
regulator-name = "tps62361-vout";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
ti,vsel0-state-high;
|
||||
ti,vsel1-state-high;
|
||||
};
|
||||
};
|
||||
|
||||
spi@7000da00 {
|
||||
|
@ -296,13 +296,7 @@ spi-flash@1 {
|
|||
};
|
||||
};
|
||||
|
||||
ahub {
|
||||
i2s@70080400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
pmc@7000e400 {
|
||||
status = "okay";
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
|
@ -314,6 +308,12 @@ pmc {
|
|||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
ahub@70080000 {
|
||||
i2s@70080400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
|
||||
|
@ -342,7 +342,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
@ -350,6 +350,19 @@ clk32k_in: clock {
|
|||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
gpled1 {
|
||||
label = "LED1"; /* CR5A1 (blue) */
|
||||
gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
gpled2 {
|
||||
label = "LED2"; /* CR4A2 (green) */
|
||||
gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
@ -453,19 +466,6 @@ sys_3v3_pexs_reg: regulator@7 {
|
|||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
gpled1 {
|
||||
label = "LED1"; /* CR5A1 (blue) */
|
||||
gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
gpled2 {
|
||||
label = "LED2"; /* CR4A2 (green) */
|
||||
gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "nvidia,tegra-audio-rt5640-beaver",
|
||||
"nvidia,tegra-audio-rt5640";
|
||||
|
|
|
@ -8,6 +8,13 @@ / {
|
|||
model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
|
||||
compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
|
||||
|
||||
sdhci@78000400 {
|
||||
status = "okay";
|
||||
power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
keep-power-in-suspend;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
@ -83,12 +90,5 @@ vdd_bl_reg: regulator@105 {
|
|||
gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000400 {
|
||||
status = "okay";
|
||||
power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
keep-power-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -8,6 +8,13 @@ / {
|
|||
model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
|
||||
compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
|
||||
|
||||
sdhci@78000400 {
|
||||
status = "okay";
|
||||
power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
keep-power-in-suspend;
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
@ -95,11 +102,4 @@ vdd_bl2_reg: regulator@106 {
|
|||
gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000400 {
|
||||
status = "okay";
|
||||
power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
keep-power-in-suspend;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -31,7 +31,7 @@ memory {
|
|||
reg = <0x80000000 0x40000000>;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie-controller@00003000 {
|
||||
status = "okay";
|
||||
pex-clk-supply = <&pex_hvdd_3v3_reg>;
|
||||
vdd-supply = <&ldo1_reg>;
|
||||
|
@ -51,7 +51,7 @@ pci@3,0 {
|
|||
};
|
||||
};
|
||||
|
||||
pinmux {
|
||||
pinmux@70000868 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&state_default>;
|
||||
|
||||
|
@ -59,8 +59,8 @@ state_default: pinmux {
|
|||
sdmmc1_clk_pz0 {
|
||||
nvidia,pins = "sdmmc1_clk_pz0";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc1_cmd_pz1 {
|
||||
nvidia,pins = "sdmmc1_cmd_pz1",
|
||||
|
@ -69,14 +69,14 @@ sdmmc1_cmd_pz1 {
|
|||
"sdmmc1_dat2_py5",
|
||||
"sdmmc1_dat3_py4";
|
||||
nvidia,function = "sdmmc1";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc3_clk_pa6 {
|
||||
nvidia,pins = "sdmmc3_clk_pa6";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc3_cmd_pa7 {
|
||||
nvidia,pins = "sdmmc3_cmd_pa7",
|
||||
|
@ -85,15 +85,15 @@ sdmmc3_cmd_pa7 {
|
|||
"sdmmc3_dat2_pb5",
|
||||
"sdmmc3_dat3_pb4";
|
||||
nvidia,function = "sdmmc3";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
|
@ -105,8 +105,8 @@ sdmmc4_dat0_paa0 {
|
|||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
dap2_fs_pa2 {
|
||||
nvidia,pins = "dap2_fs_pa2",
|
||||
|
@ -114,17 +114,17 @@ dap2_fs_pa2 {
|
|||
"dap2_din_pa4",
|
||||
"dap2_dout_pa5";
|
||||
nvidia,function = "i2s1";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
sdio3 {
|
||||
nvidia,pins = "drive_sdio3";
|
||||
nvidia,high-speed-mode = <0>;
|
||||
nvidia,schmitt = <0>;
|
||||
nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull-down-strength = <46>;
|
||||
nvidia,pull-up-strength = <42>;
|
||||
nvidia,slew-rate-rising = <1>;
|
||||
nvidia,slew-rate-falling = <1>;
|
||||
nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
|
||||
};
|
||||
uart3_txd_pw6 {
|
||||
nvidia,pins = "uart3_txd_pw6",
|
||||
|
@ -132,8 +132,8 @@ uart3_txd_pw6 {
|
|||
"uart3_rts_n_pc0",
|
||||
"uart3_rxd_pw7";
|
||||
nvidia,function = "uartc";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -302,7 +302,7 @@ temperature-sensor@4c {
|
|||
interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
tps62361 {
|
||||
tps62361@60 {
|
||||
compatible = "ti,tps62361";
|
||||
reg = <0x60>;
|
||||
|
||||
|
@ -326,13 +326,7 @@ spi-flash@1 {
|
|||
};
|
||||
};
|
||||
|
||||
ahub {
|
||||
i2s@70080400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pmc {
|
||||
pmc@7000e400 {
|
||||
status = "okay";
|
||||
nvidia,invert-interrupt;
|
||||
nvidia,suspend-mode = <1>;
|
||||
|
@ -344,6 +338,12 @@ pmc {
|
|||
nvidia,sys-clock-req-active-high;
|
||||
};
|
||||
|
||||
ahub@70080000 {
|
||||
i2s@70080400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000000 {
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
|
||||
|
@ -372,7 +372,7 @@ clocks {
|
|||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk32k_in: clock {
|
||||
clk32k_in: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
#clock-cells = <0>;
|
||||
|
|
|
@ -1,5 +1,6 @@
|
|||
#include <dt-bindings/clock/tegra30-car.h>
|
||||
#include <dt-bindings/gpio/tegra-gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
@ -16,7 +17,7 @@ aliases {
|
|||
serial4 = &uarte;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
pcie-controller@00003000 {
|
||||
compatible = "nvidia,tegra30-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0x00003000 0x00000800 /* PADS registers */
|
||||
|
@ -89,7 +90,7 @@ pci@3,0 {
|
|||
};
|
||||
};
|
||||
|
||||
host1x {
|
||||
host1x@50000000 {
|
||||
compatible = "nvidia,tegra30-host1x", "simple-bus";
|
||||
reg = <0x50000000 0x00024000>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
|
||||
|
@ -103,7 +104,7 @@ host1x {
|
|||
|
||||
ranges = <0x54000000 0x54000000 0x04000000>;
|
||||
|
||||
mpe {
|
||||
mpe@54040000 {
|
||||
compatible = "nvidia,tegra30-mpe";
|
||||
reg = <0x54040000 0x00040000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -112,7 +113,7 @@ mpe {
|
|||
reset-names = "mpe";
|
||||
};
|
||||
|
||||
vi {
|
||||
vi@54080000 {
|
||||
compatible = "nvidia,tegra30-vi";
|
||||
reg = <0x54080000 0x00040000>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -121,7 +122,7 @@ vi {
|
|||
reset-names = "vi";
|
||||
};
|
||||
|
||||
epp {
|
||||
epp@540c0000 {
|
||||
compatible = "nvidia,tegra30-epp";
|
||||
reg = <0x540c0000 0x00040000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -130,7 +131,7 @@ epp {
|
|||
reset-names = "epp";
|
||||
};
|
||||
|
||||
isp {
|
||||
isp@54100000 {
|
||||
compatible = "nvidia,tegra30-isp";
|
||||
reg = <0x54100000 0x00040000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -139,7 +140,7 @@ isp {
|
|||
reset-names = "isp";
|
||||
};
|
||||
|
||||
gr2d {
|
||||
gr2d@54140000 {
|
||||
compatible = "nvidia,tegra30-gr2d";
|
||||
reg = <0x54140000 0x00040000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -148,7 +149,7 @@ gr2d {
|
|||
clocks = <&tegra_car TEGRA30_CLK_GR2D>;
|
||||
};
|
||||
|
||||
gr3d {
|
||||
gr3d@54180000 {
|
||||
compatible = "nvidia,tegra30-gr3d";
|
||||
reg = <0x54180000 0x00040000>;
|
||||
clocks = <&tegra_car TEGRA30_CLK_GR3D
|
||||
|
@ -189,7 +190,7 @@ rgb {
|
|||
};
|
||||
};
|
||||
|
||||
hdmi {
|
||||
hdmi@54280000 {
|
||||
compatible = "nvidia,tegra30-hdmi";
|
||||
reg = <0x54280000 0x00040000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -201,7 +202,7 @@ hdmi {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
tvo {
|
||||
tvo@542c0000 {
|
||||
compatible = "nvidia,tegra30-tvo";
|
||||
reg = <0x542c0000 0x00040000>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -209,7 +210,7 @@ tvo {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
dsi {
|
||||
dsi@54300000 {
|
||||
compatible = "nvidia,tegra30-dsi";
|
||||
reg = <0x54300000 0x00040000>;
|
||||
clocks = <&tegra_car TEGRA30_CLK_DSIA>;
|
||||
|
@ -227,7 +228,7 @@ timer@50004600 {
|
|||
clocks = <&tegra_car TEGRA30_CLK_TWD>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller {
|
||||
intc: interrupt-controller@50041000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
reg = <0x50041000 0x1000
|
||||
0x50040100 0x0100>;
|
||||
|
@ -235,7 +236,7 @@ intc: interrupt-controller {
|
|||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
cache-controller {
|
||||
cache-controller@50043000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x50043000 0x1000>;
|
||||
arm,data-latency = <6 6 2>;
|
||||
|
@ -256,14 +257,14 @@ timer@60005000 {
|
|||
clocks = <&tegra_car TEGRA30_CLK_TIMER>;
|
||||
};
|
||||
|
||||
tegra_car: clock {
|
||||
tegra_car: clock@60006000 {
|
||||
compatible = "nvidia,tegra30-car";
|
||||
reg = <0x60006000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
apbdma: dma {
|
||||
apbdma: dma@6000a000 {
|
||||
compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
|
||||
reg = <0x6000a000 0x1400>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -304,12 +305,12 @@ apbdma: dma {
|
|||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
ahb: ahb {
|
||||
ahb: ahb@6000c004 {
|
||||
compatible = "nvidia,tegra30-ahb";
|
||||
reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
|
||||
};
|
||||
|
||||
gpio: gpio {
|
||||
gpio: gpio@6000d000 {
|
||||
compatible = "nvidia,tegra30-gpio";
|
||||
reg = <0x6000d000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -326,7 +327,7 @@ gpio: gpio {
|
|||
interrupt-controller;
|
||||
};
|
||||
|
||||
pinmux: pinmux {
|
||||
pinmux: pinmux@70000868 {
|
||||
compatible = "nvidia,tegra30-pinmux";
|
||||
reg = <0x70000868 0xd4 /* Pad control registers */
|
||||
0x70003000 0x3e4>; /* Mux registers */
|
||||
|
@ -405,7 +406,7 @@ uarte: serial@70006400 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm {
|
||||
pwm: pwm@7000a000 {
|
||||
compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
|
@ -415,7 +416,7 @@ pwm: pwm {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc {
|
||||
rtc@7000e000 {
|
||||
compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
|
||||
reg = <0x7000e000 0x100>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -586,7 +587,7 @@ spi@7000de00 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
kbc {
|
||||
kbc@7000e200 {
|
||||
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
|
||||
reg = <0x7000e200 0x100>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
@ -596,14 +597,14 @@ kbc {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pmc {
|
||||
pmc@7000e400 {
|
||||
compatible = "nvidia,tegra30-pmc";
|
||||
reg = <0x7000e400 0x400>;
|
||||
clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
};
|
||||
|
||||
memory-controller {
|
||||
memory-controller@7000f000 {
|
||||
compatible = "nvidia,tegra30-mc";
|
||||
reg = <0x7000f000 0x010
|
||||
0x7000f03c 0x1b4
|
||||
|
@ -612,7 +613,7 @@ memory-controller {
|
|||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
iommu {
|
||||
iommu@7000f010 {
|
||||
compatible = "nvidia,tegra30-smmu";
|
||||
reg = <0x7000f010 0x02c
|
||||
0x7000f1f0 0x010
|
||||
|
@ -622,7 +623,7 @@ iommu {
|
|||
nvidia,ahb = <&ahb>;
|
||||
};
|
||||
|
||||
ahub {
|
||||
ahub@70080000 {
|
||||
compatible = "nvidia,tegra30-ahub";
|
||||
reg = <0x70080000 0x200
|
||||
0x70080200 0x100>;
|
||||
|
|
|
@ -43,6 +43,7 @@
|
|||
#define TEGRA_GPIO_BANK_ID_CC 28
|
||||
#define TEGRA_GPIO_BANK_ID_DD 29
|
||||
#define TEGRA_GPIO_BANK_ID_EE 30
|
||||
#define TEGRA_GPIO_BANK_ID_FF 31
|
||||
|
||||
#define TEGRA_GPIO(bank, offset) \
|
||||
((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
|
||||
|
|
45
include/dt-bindings/pinctrl/pinctrl-tegra.h
Normal file
45
include/dt-bindings/pinctrl/pinctrl-tegra.h
Normal file
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* This header provides constants for Tegra pinctrl bindings.
|
||||
*
|
||||
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Author: Laxman Dewangan <ldewangan@nvidia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
|
||||
#define _DT_BINDINGS_PINCTRL_TEGRA_H
|
||||
|
||||
/*
|
||||
* Enable/disable for diffeent dt properties. This is applicable for
|
||||
* properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
|
||||
* nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
|
||||
*/
|
||||
#define TEGRA_PIN_DISABLE 0
|
||||
#define TEGRA_PIN_ENABLE 1
|
||||
|
||||
#define TEGRA_PIN_PULL_NONE 0
|
||||
#define TEGRA_PIN_PULL_DOWN 1
|
||||
#define TEGRA_PIN_PULL_UP 2
|
||||
|
||||
/* Low power mode driver */
|
||||
#define TEGRA_PIN_LP_DRIVE_DIV_8 0
|
||||
#define TEGRA_PIN_LP_DRIVE_DIV_4 1
|
||||
#define TEGRA_PIN_LP_DRIVE_DIV_2 2
|
||||
#define TEGRA_PIN_LP_DRIVE_DIV_1 3
|
||||
|
||||
/* Rising/Falling slew rate */
|
||||
#define TEGRA_PIN_SLEW_RATE_FASTEST 0
|
||||
#define TEGRA_PIN_SLEW_RATE_FAST 1
|
||||
#define TEGRA_PIN_SLEW_RATE_SLOW 2
|
||||
#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
|
||||
|
||||
#endif
|
Loading…
Reference in a new issue