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drm/amd/display: Add OTG/ODM functions
[WHY] Required for correct OTG_H_TIMING_CNTL programming Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 34 additions and 0 deletions
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@ -160,6 +160,37 @@ void optc314_phantom_crtc_post_enable(struct timing_generator *optc)
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REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000);
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}
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static void optc314_set_odm_bypass(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
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REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
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OPTC_NUM_OF_INPUT_SEGMENT, 0,
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OPTC_SEG0_SRC_SEL, optc->inst,
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OPTC_SEG1_SRC_SEL, 0xf,
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OPTC_SEG2_SRC_SEL, 0xf,
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OPTC_SEG3_SRC_SEL, 0xf
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);
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h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
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REG_UPDATE(OTG_H_TIMING_CNTL,
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OTG_H_TIMING_DIV_MODE, h_div);
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REG_SET(OPTC_MEMORY_CONFIG, 0,
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OPTC_MEM_SEL, 0);
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optc1->opp_count = 1;
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}
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static void optc314_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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REG_UPDATE(OTG_H_TIMING_CNTL,
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OTG_H_TIMING_DIV_MODE_MANUAL, manual_mode ? 1 : 0);
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}
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static struct timing_generator_funcs dcn314_tg_funcs = {
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.validate_timing = optc1_validate_timing,
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@ -222,6 +253,9 @@ static struct timing_generator_funcs dcn314_tg_funcs = {
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.setup_manual_trigger = optc2_setup_manual_trigger,
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.get_hw_timing = optc1_get_hw_timing,
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.init_odm = optc3_init_odm,
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.set_odm_bypass = optc314_set_odm_bypass,
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.set_odm_combine = optc314_set_odm_combine,
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.set_h_timing_div_manual_mode = optc314_set_h_timing_div_manual_mode,
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};
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void dcn314_timing_generator_init(struct optc *optc1)
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