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phy: qcom-qmp: move PCS V2 registers to separate header 

Move PCS V2 registers to the separate header.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-14-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov 2022-07-05 12:43:05 +03:00 committed by Vinod Koul
parent 147924ffe2
commit 5ae11aa488
2 changed files with 39 additions and 28 deletions
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38
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h Normal file
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@ -0,0 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#ifndef QCOM_PHY_QMP_PCS_V2_H_
#define QCOM_PHY_QMP_PCS_V2_H_
/* Only for QMP V2 PHY - PCS registers */
#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
#endif

29
drivers/phy/qualcomm/phy-qcom-qmp.h
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@ -20,34 +20,7 @@
#include "phy-qcom-qmp-qserdes-pll.h"
/* Only for QMP V2 PHY - PCS registers */
#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24
#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28
#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34
#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38
#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c
#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40
#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54
#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58
#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60
#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64
#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84
#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88
#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
#include "phy-qcom-qmp-pcs-v2.h"
/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00