mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-05 10:29:37 +00:00
mvebu register map changes for v3.11
This series removes the hardcoded register base address for mvebu. Depends: - mvebu/fixes-non-critical (up to tags/fixes-non-3.11-1) - mvebu/cleanup (up to tags/cleanup-3.11-3) -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.20 (GNU/Linux) iQEcBAABAgAGBQJRujY/AAoJEAi3KVZQDZAeQ/8H/186TUo1jWJJP/Tdp6Rg09qK FeZeVH9YrViLO2g2iO338TlfIjshJW8HgMv8tnuJo9xLz5wtws3Dpv5BpcYoGoKs vU/d1EZC4vJTs5IZ2fS6p0LpvV8YrUYVi9v7uPWHFx6DYGznuHPP/q8Hu6Pa0Tok MoPNAihBYMEhePGuBQo1j3xPtteifJy/CUv5iSrAAJSEI5zGRc7QO/0ItS2gc9qy odFZKTZnGPlp/79np4I1/cjNTRuD5kf/9IzNFxl4ZL4X7Nre9J+8IFoPU671EDw1 XMBEtf6ThO6Z8oLiVPxeHlSLO2o7xQj7VEAUoSEsiK4whJAfxFiOqIiIC5SXfDA= =hKzx -----END PGP SIGNATURE----- Merge tag 'regmap-3.11' of git://git.infradead.org/users/jcooper/linux into next/soc mvebu register map changes for v3.11 This series removes the hardcoded register base address for mvebu. Depends: - mvebu/fixes-non-critical (up to tags/fixes-non-3.11-1) - mvebu/cleanup (up to tags/cleanup-3.11-3) * tag 'regmap-3.11' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: disable DEBUG_LL/EARLY_PRINTK in defconfig arm: mvebu: add another earlyprintk Kconfig option arm: mvebu: don't hardcode the physical address for mvebu-mbus arm: mvebu: don't hardcode a physical address in headsmp.S arm: mvebu: remove hardcoded static I/O mapping arm: mvebu: move cache and mvebu-mbus initialization later arm: mvebu: avoid hardcoded virtual address in coherency code arm: mvebu: remove dependency of SMP init on static I/O mapping arm: mvebu: fix length of Ethernet registers area in .dtsi arm: mvebu: fix length of SATA registers area in .dtsi arm: mvebu: mark functions of armada-370-xp.c as static ARM: mvebu: Remove init_irq declaration in machine description ARM: Orion: Remove redundant init_dma_coherent_pool_size() Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
5ae13ef4e1
13 changed files with 110 additions and 84 deletions
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@ -303,12 +303,37 @@ choice
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their output to the serial port on MSM 8960 devices.
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config DEBUG_MVEBU_UART
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bool "Kernel low-level debugging messages via MVEBU UART"
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bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)"
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depends on ARCH_MVEBU
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help
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Say Y here if you want kernel low-level debugging support
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on MVEBU based platforms.
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This option should be used with the old bootloaders
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that left the internal registers mapped at
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0xd0000000. As of today, this is the case on
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platforms such as the Globalscale Mirabox or the
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Plathome OpenBlocks AX3, when using the original
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bootloader.
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If the wrong DEBUG_MVEBU_UART* option is selected,
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when u-boot hands over to the kernel, the system
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silently crashes, with no serial output at all.
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config DEBUG_MVEBU_UART_ALTERNATE
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bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)"
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depends on ARCH_MVEBU
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help
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Say Y here if you want kernel low-level debugging support
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on MVEBU based platforms.
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This option should be used with the new bootloaders
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that remap the internal registers at 0xf1000000.
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If the wrong DEBUG_MVEBU_UART* option is selected,
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when u-boot hands over to the kernel, the system
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silently crashes, with no serial output at all.
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config DEBUG_NOMADIK_UART
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bool "Kernel low-level debugging messages via NOMADIK UART"
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depends on ARCH_NOMADIK
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@ -632,7 +657,8 @@ config DEBUG_LL_INCLUDE
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DEBUG_IMX51_UART || \
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DEBUG_IMX53_UART ||\
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DEBUG_IMX6Q_UART
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default "debug/mvebu.S" if DEBUG_MVEBU_UART
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default "debug/mvebu.S" if DEBUG_MVEBU_UART || \
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DEBUG_MVEBU_UART_ALTERNATE
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default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
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default "debug/nomadik.S" if DEBUG_NOMADIK_UART
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default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
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@ -80,7 +80,7 @@ timer@20300 {
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sata@a0000 {
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compatible = "marvell,orion-sata";
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reg = <0xa0000 0x2400>;
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reg = <0xa0000 0x5000>;
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interrupts = <55>;
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clocks = <&gateclk 15>, <&gateclk 30>;
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clock-names = "0", "1";
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@ -96,7 +96,7 @@ mdio {
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ethernet@70000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x70000 0x2500>;
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reg = <0x70000 0x4000>;
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interrupts = <8>;
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clocks = <&gateclk 4>;
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status = "disabled";
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@ -104,7 +104,7 @@ ethernet@70000 {
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ethernet@74000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x74000 0x2500>;
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reg = <0x74000 0x4000>;
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interrupts = <10>;
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clocks = <&gateclk 3>;
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status = "disabled";
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@ -107,7 +107,7 @@ gpio2: gpio@18180 {
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ethernet@34000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x34000 0x2500>;
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reg = <0x34000 0x4000>;
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interrupts = <14>;
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clocks = <&gateclk 1>;
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status = "disabled";
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@ -88,7 +88,7 @@ system-controller@18200 {
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ethernet@30000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x30000 0x2500>;
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reg = <0x30000 0x4000>;
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interrupts = <12>;
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clocks = <&gateclk 2>;
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status = "disabled";
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@ -100,5 +100,3 @@ CONFIG_TIMER_STATS=y
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# CONFIG_DEBUG_BUGVERBOSE is not set
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CONFIG_DEBUG_INFO=y
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CONFIG_DEBUG_USER=y
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CONFIG_DEBUG_LL=y
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CONFIG_EARLY_PRINTK=y
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@ -11,7 +11,12 @@
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* published by the Free Software Foundation.
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*/
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#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE
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#define ARMADA_370_XP_REGS_PHYS_BASE 0xf1000000
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#else
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#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
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#endif
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#define ARMADA_370_XP_REGS_VIRT_BASE 0xfec00000
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.macro addruart, rp, rv, tmp
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@ -15,12 +15,12 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk-provider.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/io.h>
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#include <linux/time-armada-370-xp.h>
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#include <linux/dma-mapping.h>
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#include <linux/mbus.h>
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#include <linux/irqchip.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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@ -29,45 +29,49 @@
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#include "common.h"
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#include "coherency.h"
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static struct map_desc armada_370_xp_io_desc[] __initdata = {
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{
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.virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
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.length = ARMADA_370_XP_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init armada_370_xp_map_io(void)
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static void __init armada_370_xp_map_io(void)
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{
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iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
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debug_ll_io_init();
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}
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void __init armada_370_xp_timer_and_clk_init(void)
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{
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of_clk_init(NULL);
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armada_370_xp_timer_init();
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}
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/*
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* This initialization will be replaced by a DT-based
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* initialization once the mvebu-mbus driver gains DT support.
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*/
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void __init armada_370_xp_init_early(void)
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#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000
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#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
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#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180
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#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
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static void __init armada_370_xp_mbus_init(void)
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{
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char *mbus_soc_name;
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struct device_node *dn;
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const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
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const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
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/*
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* This initialization will be replaced by a DT-based
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* initialization once the mvebu-mbus driver gains DT support.
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*/
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if (of_machine_is_compatible("marvell,armada370"))
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mbus_soc_name = "marvell,armada370-mbus";
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else
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mbus_soc_name = "marvell,armadaxp-mbus";
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mvebu_mbus_init(mbus_soc_name,
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ARMADA_370_XP_MBUS_WINS_BASE,
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ARMADA_370_XP_MBUS_WINS_SIZE,
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ARMADA_370_XP_SDRAM_WINS_BASE,
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ARMADA_370_XP_SDRAM_WINS_SIZE);
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dn = of_find_node_by_name(NULL, "internal-regs");
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BUG_ON(!dn);
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mvebu_mbus_init(mbus_soc_name,
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of_translate_address(dn, &mbus_wins_offs),
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ARMADA_370_XP_MBUS_WINS_SIZE,
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of_translate_address(dn, &sdram_wins_offs),
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ARMADA_370_XP_SDRAM_WINS_SIZE);
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}
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static void __init armada_370_xp_timer_and_clk_init(void)
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{
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of_clk_init(NULL);
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armada_370_xp_timer_init();
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coherency_init();
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armada_370_xp_mbus_init();
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#ifdef CONFIG_CACHE_L2X0
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l2x0_of_init(0, ~0UL);
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#endif
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@ -76,7 +80,6 @@ void __init armada_370_xp_init_early(void)
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static void __init armada_370_xp_dt_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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coherency_init();
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}
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static const char * const armada_370_xp_dt_compat[] = {
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@ -88,8 +91,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
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.smp = smp_ops(armada_xp_smp_ops),
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.init_machine = armada_370_xp_dt_init,
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.map_io = armada_370_xp_map_io,
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.init_early = armada_370_xp_init_early,
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.init_irq = irqchip_init,
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.init_time = armada_370_xp_timer_and_clk_init,
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.restart = mvebu_restart,
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.dt_compat = armada_370_xp_dt_compat,
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@ -15,16 +15,6 @@
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#ifndef __MACH_ARMADA_370_XP_H
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#define __MACH_ARMADA_370_XP_H
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#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
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#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfec00000)
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#define ARMADA_370_XP_REGS_SIZE SZ_1M
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/* These defines can go away once mvebu-mbus has a DT binding */
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#define ARMADA_370_XP_MBUS_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
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#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
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#define ARMADA_370_XP_SDRAM_WINS_BASE (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180)
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#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
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#ifdef CONFIG_SMP
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#include <linux/cpumask.h>
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@ -25,16 +25,11 @@
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <asm/smp_plat.h>
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#include <asm/cacheflush.h>
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#include "armada-370-xp.h"
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/*
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* Some functions in this file are called very early during SMP
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* initialization. At that time the device tree framework is not yet
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* ready, and it is not possible to get the register address to
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* ioremap it. That's why the pointer below is given with an initial
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* value matching its virtual mapping
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*/
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static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
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unsigned long __cpuinitdata coherency_phys_base;
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static void __iomem *coherency_base;
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static void __iomem *coherency_cpu_base;
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/* Coherency fabric registers */
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@ -47,18 +42,6 @@ static struct of_device_id of_coherency_table[] = {
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{ /* end of list */ },
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};
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#ifdef CONFIG_SMP
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int coherency_get_cpu_count(void)
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{
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int reg, cnt;
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reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
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cnt = (reg & 0xF) + 1;
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return cnt;
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}
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#endif
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/* Function defined in coherency_ll.S */
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int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
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@ -143,13 +126,30 @@ int __init coherency_init(void)
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np = of_find_matching_node(NULL, of_coherency_table);
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if (np) {
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struct resource res;
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pr_info("Initializing Coherency fabric\n");
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of_address_to_resource(np, 0, &res);
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coherency_phys_base = res.start;
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/*
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* Ensure secondary CPUs will see the updated value,
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* which they read before they join the coherency
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* fabric, and therefore before they are coherent with
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* the boot CPU cache.
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*/
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sync_cache_w(&coherency_phys_base);
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coherency_base = of_iomap(np, 0);
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coherency_cpu_base = of_iomap(np, 1);
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set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
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bus_register_notifier(&platform_bus_type,
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&mvebu_hwcc_platform_nb);
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}
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return 0;
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}
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static int __init coherency_late_init(void)
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{
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bus_register_notifier(&platform_bus_type,
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&mvebu_hwcc_platform_nb);
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return 0;
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}
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postcore_initcall(coherency_late_init);
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@ -14,10 +14,6 @@
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#ifndef __MACH_370_XP_COHERENCY_H
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#define __MACH_370_XP_COHERENCY_H
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#ifdef CONFIG_SMP
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int coherency_get_cpu_count(void);
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#endif
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int set_cpu_coherent(int cpu_id, int smp_group_id);
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int coherency_init(void);
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@ -15,6 +15,8 @@
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#ifndef __ARCH_MVEBU_COMMON_H
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#define __ARCH_MVEBU_COMMON_H
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#define ARMADA_XP_MAX_CPUS 4
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void mvebu_restart(char mode, const char *cmd);
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void armada_370_xp_init_irq(void);
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@ -21,12 +21,6 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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/*
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* At this stage the secondary CPUs don't have acces yet to the MMU, so
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* we have to provide physical addresses
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*/
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#define ARMADA_XP_CFB_BASE 0xD0020200
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__CPUINIT
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/*
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@ -35,15 +29,21 @@
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* startup
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*/
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ENTRY(armada_xp_secondary_startup)
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/* Get coherency fabric base physical address */
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adr r0, 1f
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ldr r1, [r0]
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ldr r0, [r0, r1]
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/* Read CPU id */
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mrc p15, 0, r1, c0, c0, 5
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and r1, r1, #0xF
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/* Add CPU to coherency fabric */
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ldr r0, =ARMADA_XP_CFB_BASE
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bl ll_set_cpu_coherent
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b secondary_startup
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ENDPROC(armada_xp_secondary_startup)
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.align 2
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1:
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.long coherency_phys_base - .
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|
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@ -88,8 +88,16 @@ static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
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static void __init armada_xp_smp_init_cpus(void)
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{
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struct device_node *np;
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unsigned int i, ncores;
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ncores = coherency_get_cpu_count();
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np = of_find_node_by_name(NULL, "cpus");
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if (!np)
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panic("No 'cpus' node found\n");
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ncores = of_get_child_count(np);
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if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
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panic("Invalid number of CPUs in DT\n");
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/* Limit possible CPUs to defconfig */
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if (ncores > nr_cpu_ids) {
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