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drm/i915: Add Wa_14010733141
The WA requires the following procedure for VDBox SFC reset:
If (MFX-SFC usage is 1) {
1.Issue a MFX-SFC forced lock
2.Wait for MFX-SFC forced lock ack
3.Check the MFX-SFC usage bit
If (MFX-SFC usage bit is 1)
Reset VDBOX and SFC
else
Reset VDBOX
Release the force lock MFX-SFC
}
else if(HCP+SFC usage is 1) {
1.Issue a VE-SFC forced lock
2.Wait for SFC forced lock ack
3.Check the VE-SFC usage bit
If (VE-SFC usage bit is 1)
Reset VDBOX
else
Reset VDBOX and SFC
Release the force lock VE-SFC.
}
else
Reset VDBOX
- Restructure: the changes to the original code flow should stay
relatively minimal; we only need to do an extra HCP check after the
usual VD-MFX check and, if true, switch the register/bit we're
performing the lock on.(MattR)
v2:
- Assign unlock mask using paired_engine->mask instead of using
BIT(paired_vecs->id). (Daniele)
Bspec: 52890, 53509
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Co-developed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210526094852.286424-2-aditya.swarup@intel.com
This commit is contained in:
Aditya Swarup
Matt Roper
parent
615160334f
commit
5b26d57fdb
2 changed files with 139 additions and 65 deletions
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@ -338,15 +338,69 @@ static int gen6_reset_engines(struct intel_gt *gt,
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return gen6_hw_domain_reset(gt, hw_mask);
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}
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static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
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static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)
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{
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int vecs_id;
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GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);
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vecs_id = _VECS((engine->instance) / 2);
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return engine->gt->engine[vecs_id];
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}
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struct sfc_lock_data {
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i915_reg_t lock_reg;
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i915_reg_t ack_reg;
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i915_reg_t usage_reg;
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u32 lock_bit;
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u32 ack_bit;
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u32 usage_bit;
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u32 reset_bit;
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};
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static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,
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struct sfc_lock_data *sfc_lock)
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{
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switch (engine->class) {
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default:
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MISSING_CASE(engine->class);
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fallthrough;
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case VIDEO_DECODE_CLASS:
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sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine);
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sfc_lock->lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
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sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
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sfc_lock->ack_bit = GEN11_VCS_SFC_LOCK_ACK_BIT;
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sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine);
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sfc_lock->usage_bit = GEN11_VCS_SFC_USAGE_BIT;
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sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
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break;
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case VIDEO_ENHANCEMENT_CLASS:
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sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine);
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sfc_lock->lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
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sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine);
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sfc_lock->ack_bit = GEN11_VECS_SFC_LOCK_ACK_BIT;
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sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine);
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sfc_lock->usage_bit = GEN11_VECS_SFC_USAGE_BIT;
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sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
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break;
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}
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}
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static int gen11_lock_sfc(struct intel_engine_cs *engine,
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u32 *reset_mask,
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u32 *unlock_mask)
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{
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struct intel_uncore *uncore = engine->uncore;
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u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
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i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
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u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
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i915_reg_t sfc_usage;
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u32 sfc_usage_bit;
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u32 sfc_reset_bit;
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struct sfc_lock_data sfc_lock;
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bool lock_obtained, lock_to_other = false;
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int ret;
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switch (engine->class) {
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@ -354,53 +408,72 @@ static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
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if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
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return 0;
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sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
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sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
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sfc_forced_lock_ack = GEN11_VCS_SFC_LOCK_STATUS(engine);
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sfc_forced_lock_ack_bit = GEN11_VCS_SFC_LOCK_ACK_BIT;
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sfc_usage = GEN11_VCS_SFC_LOCK_STATUS(engine);
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sfc_usage_bit = GEN11_VCS_SFC_USAGE_BIT;
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sfc_reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
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break;
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fallthrough;
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case VIDEO_ENHANCEMENT_CLASS:
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sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
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sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
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get_sfc_forced_lock_data(engine, &sfc_lock);
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sfc_forced_lock_ack = GEN11_VECS_SFC_LOCK_ACK(engine);
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sfc_forced_lock_ack_bit = GEN11_VECS_SFC_LOCK_ACK_BIT;
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sfc_usage = GEN11_VECS_SFC_USAGE(engine);
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sfc_usage_bit = GEN11_VECS_SFC_USAGE_BIT;
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sfc_reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
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break;
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default:
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return 0;
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}
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if (!(intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & sfc_lock.usage_bit)) {
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struct intel_engine_cs *paired_vecs;
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if (engine->class != VIDEO_DECODE_CLASS ||
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!IS_GEN(engine->i915, 12))
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return 0;
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/*
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* Wa_14010733141
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*
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* If the VCS-MFX isn't using the SFC, we also need to check
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* whether VCS-HCP is using it. If so, we need to issue a *VE*
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* forced lock on the VE engine that shares the same SFC.
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*/
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if (!(intel_uncore_read_fw(uncore,
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GEN12_HCP_SFC_LOCK_STATUS(engine)) &
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GEN12_HCP_SFC_USAGE_BIT))
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return 0;
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paired_vecs = find_sfc_paired_vecs_engine(engine);
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get_sfc_forced_lock_data(paired_vecs, &sfc_lock);
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lock_to_other = true;
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*unlock_mask |= paired_vecs->mask;
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} else {
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*unlock_mask |= engine->mask;
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}
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/*
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* If the engine is using a SFC, tell the engine that a software reset
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* If the engine is using an SFC, tell the engine that a software reset
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* is going to happen. The engine will then try to force lock the SFC.
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* If SFC ends up being locked to the engine we want to reset, we have
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* to reset it as well (we will unlock it once the reset sequence is
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* completed).
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*/
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if (!(intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit))
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return 0;
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rmw_set_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
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rmw_set_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
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ret = __intel_wait_for_register_fw(uncore,
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sfc_forced_lock_ack,
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sfc_forced_lock_ack_bit,
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sfc_forced_lock_ack_bit,
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sfc_lock.ack_reg,
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sfc_lock.ack_bit,
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sfc_lock.ack_bit,
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1000, 0, NULL);
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/* Was the SFC released while we were trying to lock it? */
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if (!(intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit))
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/*
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* Was the SFC released while we were trying to lock it?
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*
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* We should reset both the engine and the SFC if:
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* - We were locking the SFC to this engine and the lock succeeded
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* OR
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* - We were locking the SFC to a different engine (Wa_14010733141)
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* but the SFC was released before the lock was obtained.
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*
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* Otherwise we need only reset the engine by itself and we can
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* leave the SFC alone.
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*/
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lock_obtained = (intel_uncore_read_fw(uncore, sfc_lock.usage_reg) &
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sfc_lock.usage_bit) != 0;
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if (lock_obtained == lock_to_other)
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return 0;
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if (ret) {
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@ -408,7 +481,7 @@ static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
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return ret;
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}
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*hw_mask |= sfc_reset_bit;
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*reset_mask |= sfc_lock.reset_bit;
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return 0;
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}
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@ -416,28 +489,19 @@ static void gen11_unlock_sfc(struct intel_engine_cs *engine)
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{
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struct intel_uncore *uncore = engine->uncore;
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u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
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i915_reg_t sfc_forced_lock;
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u32 sfc_forced_lock_bit;
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struct sfc_lock_data sfc_lock = {};
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switch (engine->class) {
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case VIDEO_DECODE_CLASS:
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if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
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return;
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sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
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sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
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break;
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case VIDEO_ENHANCEMENT_CLASS:
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sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
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sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
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break;
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default:
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if (engine->class != VIDEO_DECODE_CLASS &&
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engine->class != VIDEO_ENHANCEMENT_CLASS)
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return;
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}
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rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
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if (engine->class == VIDEO_DECODE_CLASS &&
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(BIT(engine->instance) & vdbox_sfc_access) == 0)
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return;
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get_sfc_forced_lock_data(engine, &sfc_lock);
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rmw_clear_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit);
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}
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static int gen11_reset_engines(struct intel_gt *gt,
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@ -456,23 +520,23 @@ static int gen11_reset_engines(struct intel_gt *gt,
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};
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struct intel_engine_cs *engine;
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intel_engine_mask_t tmp;
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u32 hw_mask;
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u32 reset_mask, unlock_mask = 0;
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int ret;
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if (engine_mask == ALL_ENGINES) {
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hw_mask = GEN11_GRDOM_FULL;
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reset_mask = GEN11_GRDOM_FULL;
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} else {
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hw_mask = 0;
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reset_mask = 0;
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for_each_engine_masked(engine, gt, engine_mask, tmp) {
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GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
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hw_mask |= hw_engine_mask[engine->id];
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ret = gen11_lock_sfc(engine, &hw_mask);
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reset_mask |= hw_engine_mask[engine->id];
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ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);
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if (ret)
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goto sfc_unlock;
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}
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}
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ret = gen6_hw_domain_reset(gt, hw_mask);
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ret = gen6_hw_domain_reset(gt, reset_mask);
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sfc_unlock:
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/*
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@ -480,10 +544,14 @@ static int gen11_reset_engines(struct intel_gt *gt,
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* gen11_lock_sfc to make sure that we clean properly if something
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* wrong happened during the lock (e.g. lock acquired after timeout
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* expiration).
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*
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* Due to Wa_14010733141, we may have locked an SFC to an engine that
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* wasn't being reset. So instead of calling gen11_unlock_sfc()
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* on engine_mask, we instead call it on the mask of engines that our
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* gen11_lock_sfc() calls told us actually had locks attempted.
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*/
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if (engine_mask != ALL_ENGINES)
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for_each_engine_masked(engine, gt, engine_mask, tmp)
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gen11_unlock_sfc(engine);
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for_each_engine_masked(engine, gt, unlock_mask, tmp)
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gen11_unlock_sfc(engine);
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return ret;
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}
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@ -416,6 +416,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
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#define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
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#define GEN12_HCP_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x2910)
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#define GEN12_HCP_SFC_FORCED_LOCK_BIT REG_BIT(0)
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#define GEN12_HCP_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x2914)
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#define GEN12_HCP_SFC_LOCK_ACK_BIT REG_BIT(1)
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#define GEN12_HCP_SFC_USAGE_BIT REG_BIT(0)
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#define GEN12_SFC_DONE(n) _MMIO(0x1cc00 + (n) * 0x100)
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#define GEN12_SFC_DONE_MAX 4
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